Specifications

VSA Mode Diagnostics
This chapter describes the board’s initialization into VSA mode and the Tests that can be run
from VSA mode. For details of the VSA command line interface, refer to Chapter 10.
Some of these tests are described to be run when the board is fitted with additional test
hardware at the factory, or in conjunction with other boards. When these tests are run by the
user, they may fail simply because this additional hardware is not available.
Some of the text descriptions below refer to “interconnect” registers. These are locations in
shared memory on the Concurrent Technologies boards operating in VSA mode, and are used
extensively for inter-board communication and control.
Several of the descriptions refer to a Soak Test Master board, which is a specialized product
used in factory testing of the boards. Tests requiring this board will not usually produce valid
results when they are run in the application systems.
11.1 Initialization Checks
The board will always start executing PC BIOS firmware; however, if the MODE switch is set to
the VSA position the BIOS will transfer control to the VSA firmware once it has completed
chipset initialization, cache and memory sizing.
The VSA firmware performs additional hardware initialization and some basic functional checks
before switching to Protected Mode and entering its master or slave test handler. These
functional checks are described below.
11.1.1 Check 16: CPU Alive Check
To test the basic CPU-interconnect access path, the CPU writes the ID of this test to the BIST
TEST ID Interconnect register, then reads it back to verify that it was correctly written.
The test fails if the value read is not the same as the value written.
11.1.2 Check 18: Scratchpad RAM Check
The first 192 Kbytes of RAM, the scratchpad, are used by the BIST firmware. This memory area
is tested by writing and verifying two rotating test patterns across the scratchpad address range.
The first pattern is 0AA55h, the second 055AAh. Each pattern is rotated left two bit positions for
each increment of the address; this ensures that consecutive addresses have unique data
patterns whether they use 16-, 32- or 64-bit bus fetches.
NOTE This is the only test carried out on this area of RAM - all other BISTs test only the
remaining RAM area.
VP 110/01x 11-1