Specifications

8.3 Status & Control Register 1(I/O address 212h)

765 43 2 1 0

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FRONT UNIVERSE VME BUS VME BUS PCI PCI PMC PMC

PANEL LINT1 ERROR ERROR EXP’N EXP’N SITE 2 SITE 1

NMI NMI FLAG INTERRUPT SLOT 2 SLOT 1

ENABLE

Bits3-0:PMCMode 1 Status of PMC Modules (Read Only)

Bit0and1=OnBoard PMC Site 1 & 2; Bits 3 and 2 = Expansion PMC Sites

0 = PCI compliant module not fitted

1 = PCI compliant module fitted

Bit 4: VME Bus Error Interrupt Enable (Read/Write)

0 = VME bus error interrupt disabled

1 = VME bus error interrupt enabled

Bit 5: VME Bus Error Flag (Read/Clear)

The flag is set by a bus error occurring during a cycle in which the Universe is the VME bus

master. The bit can be cleared by writing to the register with a zero in this bit position. This

should be done as part of the VME bus error interrupt routine.

0 = VME bus error has not occurred

1 = VME bus error has occurred

Bit 6: LINT1 from the Universe is the cause of NMI (Read Only)

This bit is set by the Universe and should be cleared by writing to the appropriate Universe

0 = LINT1 has not occurred

1 = LINT1 has occurred

Bit 7: Front Panel Switch is the cause of NMI (Read/Clear)

This bit can be cleared by writing to the register with a zero in this bit position.

0 = FP Switch NMI has not occurred

1 = FP Switch NMI has occurred

VP 110/01x 8-5

Additional Local I/O Functions