Specifications

8.2 Status & Control Register 2 (I/O address 211h)

NOTE Bit 4 of this register is device locked.

765 43 2 1 0

|________|________|_________|________|_________|_________|_________|_________|

||| || | | |

PC BUS BIOS THERM SPEED DEV DEV DEV DEV

CLOCK VSA ALERT STEP UNLOCK UNLOCK UNLOCK UNLOCK

SELECT ENABLE 3210

Bits3-0:Device Lock (Write Only)

These bits control the Device Lock function. The device lock forces various Status and Control

software should write 0X5h then 0XAh to this register.

Bit 4: SpeedStep (Read/Write Once)

0 = Low speed (battery optimized mode)

1 = High speed (performance mode)

This bit controls the logic that changes the processor operating frequency and voltage. This bit

will only respond to the first write to this register following a power-on or reset. Subsequent

writes to this register will not affect this bit.

NOTE This feature is reserved for use by the BIOS only. User software may read this bit

(to determine the operating frequency) but may not change it.

Bit 5: Therm Alert Enable (Read/Write once)

0 = Therm Alert Disabled (Default)

1 = Therm Alert Enabled

This bit controls the logic that will turn the processor off if an over temperature condition occurs

in the processor chip. The MAX1617 which monitors the processor temperature is preset by the

BIOS to trip at a safe maximum level. The trip level should not be changed.

Bit 6: BIOS/VSA Select (Read/Write )

0 = BIOS ROM selected

1 = VSA ROM selected

This bit controls the selection of the BIOS or VSA ROMs. Normal operation requires that the

BIOS ROM be selected. VSA ROM selection is used for factory test.

Bit 7: P2 PCI Bus Speed (Read Only).

0 = 33MHz operation (VIO=5V)

1 = 66MHz operation (VIO=3.3V)

This bit directly reflects status of the P2_M66EN pin of the PMC PCI bus (bus 1).

8-4 VP 110/01x

Additional Local I/O Functions