Specifications

5.3 VME Bus Error Interrupt
The VP 110/01x contains hardware to detect bus errors for VME bus cycles in which the
Universe is the bus master. The hardware is controlled by Status and Control Register 1 (see
Section 8.3). The bus error interrupt is connected to the Universe LINT0 interrupt, so software to
deal with the VME bus error interrupt can be added to the normal Universe interrupt handler.
5.4 VME Address Capture
The VP 110/01x provides hardware that captures the VME address and upon a VME Bus Error
cycle. The captured data consists of the A31-A0, DS1-0, AM5-0, LWord and WR signal states.
A single I/O register controls this function. The register provides access to the captured
information via a series of read cycles as shown in Table 5-1. Three control bits are also
defined, which permit the capture mode to be enabled, the read sequence to be reset and a
capture to be aborted.
The Bus Error event may be detected by means of the Bus Error Interrupt or by polling the VME
Address Capture status bit. When using the Bus Error Interrupt with the VME Address Capture,
these functions must be enabled together and outside the monitored transfer. This will permit
both functions to detect the Bus Error event.
The VME Bus Error Interrupt does not have to be enabled for the VME Address Capture to
operate. The VME Address Capture Function must be enabled via bit 0 of the VME Address
Capture Control register.
To ensure the VME address information is read from the start following a capture, the read data
sequence must be reset back to the start prior to the read activity. The internal read sequence
counter is advanced for every read of the VME Address Capture Status register. To reset the
read sequence a write of 0x02 is performed to the control register.
The VME address information is valid when the Capture Status bits indicates Idle following a
Bus Error event. A read of the VME address at any other time or following a capture abort is
invalid.
VME Interface
VP 110/01x 5-3