Technical Reference Manual for VP 110/01x VME Pentium® III-M Single Board Computer Manual Order Code 550 0014 Rev 02 Concurrent Technologies Inc 3840 Packard Road Suite 130 Ann Arbor, MI 48108 USA Tel: (734) 971 6309 Fax: (734) 971 6350 E-mail: info@gocct.com August 2002 Concurrent Technologies Plc 4 Gilberd Court Newcomen Way Colchester, Essex CO4 9WN United Kingdom Tel: (+44) 1206 752626 Fax: (+44) 1206 751116 http://www.gocct.
NOTES Information furnished by Concurrent Technologies is believed to be accurate and reliable. However, Concurrent Technologies assumes no responsibility for any errors contained in this document and makes no commitment to update or to keep current the information contained in this document. Concurrent Technologies reserves the right to change specifications at any time without notice.
GLOSSARY OF TERMS BIOS · · · · · Basic Input Output System BIST · · · · · Built In Self Test BSB· · · · · · Back Side Bus CCT· · · · · · Concurrent Technologies CPU · · · · · Central Processing Unit CRT· · · · · · Cathode Ray Tube DDC · · · · · Display Data Channel DIB · · · · · · Dual Independent Bus DFP· · · · · · Digital Flat Panel DMA · · · · · Direct Memory Access ECC · · · · · Error Checking and Correcting ECP· · · · · · Extended Capabilities Port EIDE · · · · · Enhanced Integrated Drive Electronics E
NOTATIONAL CONVENTIONS NOTE Notes provide general additional information. WARNING Warnings provide indication of board malfunction if they are not observed. CAUTION Cautions provide indications of board or system damage if they are not observed.
Revision Revision History Date 01 Initial Release July 2002 02 Added clarifications to several sections August 2002 VP 110/01x v
Table of Contents 1. Introduction and Overview 1.1 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.2.14 1.2.15 1.2.16 1.2.17 1.3 2. 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.6 2.7 2.8 2.9 2.9.1 2.9.2 3.
4.3 4.4 5.
10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.3.1 10.3.2 10.3.3 11.
11.2.33 11.2.34 11.2.35 11.2.35.1 11.2.35.2 11.2.35.3 11.2.35.4 11.2.35.5 11.2.35.6 11.2.36 11.2.36.1 11.2.36.2 11.2.36.3 11.2.36.4 11.2.36.5 11.2.37 11.2.38 11.2.39 11.2.39.1 11.2.39.2 11.2.39.3 11.2.40 11.2.41 11.2.42 11.2.43 11.2.44 11.2.45 11.2.46 11.2.47 11.2.48 11.2.49 11.2.50 11.2.51 A. Specifications· A.1 A.2 A.2.1 A.2.2 A.3 A.4 A.4.1 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 A.5.7 A.5.8 A.5.9 A.5.10 A.5.11 B.
B.3.1 B.3.2 B.4 B.4.1 B.4.2 B.5 B.5.1 B.5.2 B.
Table of Figures Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 6-1 Figure 7-1 Figure 7-2 Figure 7-3 Figure 8-1 Figure 9-1 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure B-1 Figure B-2 Figure B-3 VP 110/01x Overview · · · · · · · · · · · · Default Jumper and Switch Settings · · · · Front Panel Indicators and Controls · · · · Front Panel Reset and NMI Switch · · · · Mass Storage Connector and Fixing
Table of Tables Table 1-1 Table 5-1 Table 5-2 Table 5-2 Table 8-1 Table 9-1 Table 9-2 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table B-1 Table B-2 Table B-3 Table B-4 Table B-5 Table B-6 Table B-7 xii VME P2 Breakout Interfaces · · · · · · · VME Address Capture Read Register· · · · · VME Address Modifier Codes · · · · · · · VME Address Modifier Codes (Continue
Introduction and Overview 1.1 General This manual is a guide and reference handbook for engineers and system integrators who wish to use the Concurrent Technologies’ VP 110/01x ultra high-performance Pentium III Processor-M (Pentium III-M) single board computer. The board has been designed for high-speed multiprocessing applications using a PC-AT™ architecture operating in a VME Bus environment.
Introduction and Overview 1.2 The VP 110/01x - Main Features The VP 110/01x is a member of the Concurrent Technologies range of single-board computers for the VME bus architecture. It has been designed as a powerful single board computer based upon the Pentium III Processor-M (Pentium III-M) incorporating the following features: l up to 1 Gbyte 133MHz SDRAM l two IEEE P1386.
Introduction and Overview 1.2.4 SDRAM The on-board SDRAM operates at 133MHz and features ECC data protection. The board is fitted with 512 Mbytes of soldered-on SDRAM. A 144-pin SODIMM socket is provided for memory expansion. This accepts a standard PC133 SDRAM module having a capacity up to 512 Mbytes. Hence a maximum of 1 Gbyte of SDRAM may be fitted to the board. 1.2.5 PCI Busses There are two on-board PCI busses supported by the CNB30LE North Bridge.
Introduction and Overview 1.2.14 Floppy Disk A floppy disk interface is provided by the Super I/O Controller for up to two floppy drives and is connected via the P2 connector. 1.2.15 Serial Communication The VP 110/01x has one RS232 serial data communication channel, accessible via a front panel mounted RJ45 connector. This connects to channel 1 of the Super I/O Controller providing a 16550 compatible Serial Communications Controller. The baud rate clock is generated internally by the Super I/O Controller.
Introduction and Overview 1.3 Additional Board Options Two on-board mass storage options are available, namely; l A 2.5” EIDE hard disk drive of at least 10 Gbyte capacity. l A CompactFlash carrier that supports the IBM® Microdrive™. Only one of these mass storage options may be fitted at a time. Refer to the VP 110/01x datasheet for ordering information. The VP 110/01x board may be ordered with one of a few different VME P2 and P0 connector breakout or adapter modules.
Introduction and Overview This page has been left intentionally blank 1-6 VP 110/01x
Hardware Installation 2.1 General This chapter contains general information on unpacking and inspecting the VP 110/01x after shipment, and information on how to configure board options and install the board into a VME chassis. CAUTION It is strongly advised that, when handling the VP 110/01x and its associated components, the user should at all times wear an earthing strap to prevent damage to the board as a result of electrostatic discharge.
Hardware Installation 2.2 Unpacking and Inspection Immediately after the board is delivered to the user’s premises the user should carry out a thorough inspection of the package for any damage caused by negligent handling in transit. CAUTION If the packaging is badly damaged or water-stained the user must insist on the carrier’s agent being present when the board is unpacked. Once unpacked, the board should be inspected carefully for physical damage, loose components etc.
Hardware Installation 2.3 Default Jumper Settings 1 2 3 4 Not Used Front Panel Switch Function - Reset 1 2 3 4 VGA Console Mode Mode - BIOS User Switch - ‘1’ Watchdog - Disabled Section 6.1 & 6.2 Section 9.1 Section 8.1 Section 8.4 Section 2.4.6 LK4 PMC V(I/O) 5V Section 2.8 LK5 CMOS Clear Normal Section 2.7 LK2 Flash Program Enabled Section 7.3 LK3 SRAM Backup Power Battery Section 7.
Hardware Installation 2.4 Front Panel Indicators and Controls When installing or removing the board for the first time, or when checking it’s operation, it can be very useful to note the behavior of the LEDs on the front panel. Figure 2-2 shows the location of the LEDs, and their purpose is outlined below. PMC Site 2 Battery (Yellow) Run (Green) Ethernet CH1 LED LED COM1 PMC Site 1 Ethernet CH0 Ground External Reset/NMI POST (Yellow) LED Switch Reset Figure 2-2 Front Panel Indicators and Controls 2.
Hardware Installation OFF 1 2 3 4 ON Switch 3 - Front Panel Switch Function ON - Reset (Default) OFF - No Action Switch 4 - Front Panel Switch Function ON - NMI OFF - No Action (Default) Figure 2-3 Front Panel Reset and NMI Switch Selecting the Reset jumper position will cause the board to be reset when the front panel switch is operated. If the board is in the System Controller Slot, it will also assert RST# on the VME backplane and hence reset the other boards in the chassis.
Hardware Installation 2.5 Installation of On-Board Mass Storage If an on-board mass storage option has been ordered, it will be necessary to install the option at this time. The mass storage option plugs into the 44-way header S1 and is secured via screws and spacers using the four mounting holes as shown in Figure 2-4 below.
Hardware Installation 2.5.1 Hard Disk Storage Kit (AD CP1/DR1) The option kit comprises: l A 2.5” EIDE disk drive. l A ribbon cable assembly. l Four M3 x 10mm screws. l Four M3 x 5mm spacers. The ribbon cable assembly has a 50-way connector at one end and a 44-way connector at the other end. The 50-way connector plugs into the disk drive and the 44-way plugs into S1 on the VP 110/01x. 1) Plug the 50-way connector into the disk drive as shown in Figure 2-5 below, note the orientation.
Hardware Installation 2.5.2 CompactFlash Storage Kit (AD 200/001) The option kit comprises: l A CompactFlash carrier module. l Four M3 panhead screws. CompactFlash Carrier Module CompactFlash Sites Site 2 Site 1 Pillars S1 Figure 2-6 CompactFlash Carrier Module Installation 1) The M3 panhead screws may be loosely screwed into the end of the pillars, if so unscrew them. NOTE Do not unscrew the countersunk screws attaching the pillars to the circuit board.
Hardware Installation 2.6 Adding or Replacing DRAM Modules The VP 110/01x accepts standard 144-pin SODIMM modules fitted with 3.3V PC133 DRAM. One socket is provided and will accommodate SODIMMs of 256 Mbytes and 512 Mbytes capacities. NOTE SODIMMs using 256Mbit DRAMs with 8K refresh are required. Figure 2-7 shows shows the way in which SODIMMs are fitted or removed. No other changes are necessary when a SODIMM is added or removed.
Hardware Installation 2.7 Installing and Replacing the Battery The on-board Real-Time Clock, CMOS memory and Non-volatile SRAM are powered by a 3.3V Lithium battery when the board is powered off. It is advisable, though not essential, for the battery to be fitted prior to using the board. Figure 2-8 shows how to do this. One battery is supplied with the board, but it is not normally fitted.
Hardware Installation CAUTION When replacing the battery, proper anti-static precautions must be observed. WARNING Dispose of battery properly. DO NOT BURN. If the battery is disconnected with out any other power, the date and time settings will need to be initialized and SRAM data will be lost. If the BIOS setup screens have been used to set up the board for an invalid configuration, or in other fault conditions, it may be useful to be able to reset the contents of the CMOS RAM and Real-Time Clock.
Hardware Installation 2.8 Installing or Removing a PMC Module Before installing a PMC module, check that the VP 110/01x board PMC V(I/O) voltage is configured to match the requirements of the PMC module. If two PMC modules are fitted, their V(I/O) requirements must be the same. CAUTION If the VP 110/01x is not correctly configured to match the PMC module V(I/O) requirements, it may result in damage to the module or the VP 110/01x.
Hardware Installation 3.3V V(I/O) Key LK4 PMC V(I/O) 5V = or 5V keys 3.3V = or 3.
Hardware Installation 2.9 Installing the Board in a VME Backplane Before the board is installed in a VME chassis, check the following points: For backplanes that do not have P0 fitted:l If you have a variant of the VP 110/01x fitted with a P0 connector, then check to see that no strengthening bars or other tall objects are present on the backplane before inserting the board.
Software Installation In most cases, installing operating system software on the VP 110/01x board follows the same sequence as installing on a PC. However, there are some additional points to note. The sections below summarize the special actions required for a few common operating systems. All but VxWorks require that a PMC VGA adapter is fitted for the duration of the installation process. 3.
Software Installation 3.2 Bootloading from CD-ROM Operating systems which install on the target hardware will generally install from CD-ROM, or may require both a CD-ROM and floppy disk. Bootloading from floppy disk requires no special steps other than to connect the drive using an appropriate cable. To bootload from CD-ROM, use the following procedure: 3-2 1) While the BIOS is running its memory test, press the key. 2) Wait for the pop-up boot device menu to be displayed.
Software Installation 3.3 Installing Windows NT® 4.0 To install Windows NT from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. 1) Obtain the Ethernet driver from the Intel web site, starting from the following address: http://developer.intel.com/design/network/drivers and selecting the 82551ER and 82559ER NDIS4 drivers.
Software Installation 3.4 Installing Windows® 2000 To install Windows 2000 from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. 1) Obtain the Ethernet driver from the Intel web site, starting from the following address: http://developer.intel.com/design/network/drivers and selecting the 82551ER and 82559ER NDIS4 drivers.
Software Installation 3.5 Installing RedHat® Linux® 7.2 To install RedHat Linux 7.2 from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. 1) Follow the standard RedHat installation instructions, but at the screen following the selection of monitor type, ensure that a “Text” login type is selected. This prevents the system from automatically starting the X11 window software.
Software Installation 3.6 Using VxWorks 5.4 with Tornado 2 Applications using this operating system are not developed on the target hardware. Concurrent Technologies can supply on request a separate Board Support Package (BSP) for this board and many others. Read the “readme” file provided with this package for details of how to configure and run VxWorks on the VP 110/01x board.
Mass Storage Interfaces The VP 110/01x board has three interfaces which can be used to attach mass storage devices: l a floppy disk interface is accessible via the VME P2 connector. l a Primary EIDE (ATA100) interface is accessible via the VME P2 connector. l a Secondary EIDE (ATA100) interface supporting on-board Mass Storage option kits. In addition, the Application Flash EPROM may be configured to operate as a ROM disk and the Battery Backed SRAM configured to operate as a RAM disk.
Mass Storage Interfaces 4.2 EIDE Interfaces The board supports two EIDE (ATA100) interfaces. The Primary EIDE interface connects via the CompactPCI J5 connector of the PP 110/01x board, or through the Transition Module. Up to two EIDE peripherals may be connected to this interface. The BIOS Setup screens, for Main | Primary Master and Main | Primary Slave allow the user to see what is connected to this interface, and to select some characteristics of the drives manually.
Mass Storage Interfaces 4.3 ROM Disk The BIOS can optionally provide a ROM disk, which uses the Application Flash Memory to store user code and data in a robust, but easily accessible format. Either Drive A: or B: may be configured as a ROM disk via the BIOS Setup screen: Main|ROM/RAM Disk (A:) or Main|ROM/RAM Disk (B:). When Drive A: is configured as a ROM disk it may also be configured as a boot device using the Boot Device Selection menu (see Section 9.
Mass Storage Interfaces 4.4 RAM Disk The BIOS can optionally provide a RAM disk, which uses the Battery-Backed SRAM to store user code and data in a robust, but easily accessible format that is also writeable without the need to erase and program flash memory. Drive B: may be configured as a RAM disk via the BIOS Setup screen: Main|ROM/RAM Disk (B:). The original floppy Drive B: will no longer be accessible.
VME Interface The VP 110/01x board is fitted with a Tundra Universe II PCI-to-VME bus bridge device together with additional support logic. This hardware implements a flexible interface to and from the VME bus with the following key characteristics. 5.1 VME Bus Interface Features The VP 110/01x can be programmed as a VME master supporting off-board VME memory addressing accessible by any PCI bus master.
VME Interface 5.2 VME Byte Swapping The VP 110/01x provides hardware that performs fast byte swapping for aligned D16, D32 and D64 VME transfers. Byte swapping can be enabled separately for master and slave transfers under software control, using Status & Control Register 0 (see Section 9.1 for further details). Swapping is performed as follows:D16 (Double Byte 2 - 3): D[31...24] D[23...16] < - > < - > D[23...16] D[31...24 < - > < - > D[7.....0] D[15....8] < < < < - > > > > D[7....0] D[15....
VME Interface 5.3 VME Bus Error Interrupt The VP 110/01x contains hardware to detect bus errors for VME bus cycles in which the Universe is the bus master. The hardware is controlled by Status and Control Register 1 (see Section 8.3). The bus error interrupt is connected to the Universe LINT0 interrupt, so software to deal with the VME bus error interrupt can be added to the normal Universe interrupt handler. 5.
VME Interface 5.4.1 VME Address Capture Read Register (Read Only) 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | CAPTURE RFU RFU RFU SD3 SD2 SD1 SD0 STATUS Bit 3-0: Captured Address The VME address is sequentially read as follows following a captured bus error event.
VME Interface AM05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 AM04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 AM03 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 AM02 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 AM01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 AM00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VME Interface AM05 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AM04 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AM03 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AM02 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AM01 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AM00 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hex 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access Type A16 non-privileged RFU RFU A16 lock command (LCK) A16 supervisory RFU Control/Status register RFU RF
Other Interfaces Many additional standard interfaces are provided on the VP 110/01x board. These interfaces consist primarily of those found in a regular desktop or mobile PC, and are outlined below. 6.1 Serial Port A single RS232 serial interface is provided, and connects via the front panel The front panel connector is an RJ45 type, and an adapter cable is required to convert to a D-type connector of the appropriate size and gender.
Other Interfaces 6.2 Keyboard and Mouse Ports A single 8-way x 0.1 inch, board mounted header provides connections for a PC keyboard and a PS/2 mouse. The pin-out of the front panel connector is detailed in Section A.5.4. Power for the keyboard and mouse interfaces is protected by a 0.75A self-resetting current limiting circuit. To reset this circuit power the board off, remove and replace the faulty keyboard or mouse device, then power up again.
Other Interfaces 6.3 Ethernet Controllers The VP 110/01x supports two 10/100Mbits Ethernet interfaces via two RJ45 connectors on the front panel. The interfaces are provided by two Intel 82559ER devices. These interfaces are pre-configured in the factory with unique IEEE addresses which are identified by two labels fixed to the board. Two LEDs are associated with each interface to indicate connection speed (yellow LED) and link activity (green LED).
Other Interfaces 6.4 Real-Time Clock A conventional PC Real-Time Clock is included on this board. This is Year 2000 compliant and can be powered by an additional Lithium battery when main power to the board is removed. See Section 2.7 for more details of how to fit or replace the battery. The Clock device also provides 256 bytes of CMOS RAM, in which the PC BIOS keeps much of its setup screen data and other information.
Other Interfaces 6.5 Universal Serial Bus (USB) A single USB 1.0 interface is provided on this board, and is accessed via the VME P2 connector or a Breakout Module. This channel can operate at 1.5Mbits/s or 12Mbits/s.
Other Interfaces 6.6 Power On Self Test LED/Speaker The Power On Self Test (POST) LED is connected to the PC Speaker port. The LED will light when the speaker port is driven. The VP 110/01x is not fitted with an audio/speaker output.
Memory The board supports several combinations of the following memory: l SDRAM l BIOS/VSA Flash EPROM l StrataFlash EPROM l Battery backed SRAM The specific memory provision is determined by suffixes to the part number.
Memory 7.1 SDRAM The VP 110/01x board supports a large amount of ECC SDRAM. 512 Mbytes is soldered onto the board, and a single 144-pin SODIMM site allows an additional 256 Mbytes or 512 Mbytes to be fitted either at the factory or in the field, giving a maximum size of 1 Gbyte. Section 2.6 describes how to fit this SODIMM, and details the types supported. The SDRAM can be accessed from both the local PCI bus and the VME backplane.
Memory 7.2 Flash EPROM The VP 110/01x has two Flash EPROM parts: the first is installed in a socket and is programmed at the factory with PC BIOS firmware. This EPROM will not normally be reprogrammed by the user, but Concurrent Technologies has programming software which allows BIOS updates to be carried out in the field when necessary, perhaps to add new features.
Memory 7.3 Application Flash EPROM The board is fitted with between 16 and 64 Mbytes of Intel StrataFlash EPROM which is free for use by application software. The memory is connected to the CSB5 X-Bus interface and is accessible in protected mode via a paged 512 Kbyte window (refer to Figure 7-1). This window is shared with the battery backed SRAM. Memory allocated to the window is selected via a combination of device and page within that device. Two dedicated I/O registers provide these functions.
Memory 7.4 Battery backed SRAM The board can be fitted with 512K to 2 Mbytes of Static RAM. This SRAM is non volatile as data can be automatically retained via the on-board battery when the board is not powered. The memory is connected to the CSB5 X-Bus interface and is accessible via a paged 512 Kbyte window (refer to Figure 7-1). Memory allocated to the window is selected via a combination of device and page within that device. Two dedicated registers provide these functions.
Memory This page has been left intentionally blank 7-6 VP 110/01x
Additional Local I/O Functions The VP 110/01x supports a variety of I/O functions whose addresses are summarized in Table 8-1.
Additional Local I/O Functions There are 13 byte wide status and control registers.
Additional Local I/O Functions 8.1 Status & Control Register 0 (I/O address 210h) 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | CONSOLE USER BYTE BYTE BYTE BOARD BOARD BOARD SWITCH SWITCH SWAP SWAP SWAP REV 2 REV 1 REV 0 Bits 2 - 0: Hardware Revision Strapping (Read Only) 000 = Rev A 001 = Rev B Etc...
Additional Local I/O Functions 8.2 Status & Control Register 2 (I/O address 211h) NOTE Bit 4 of this register is device locked. 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | PC BUS BIOS THERM SPEED DEV DEV DEV DEV CLOCK VSA ALERT STEP UNLOCK UNLOCK UNLOCK UNLOCK SELECT ENABLE 3 2 1 0 Bits 3 - 0: Device Lock (Write Only) These bits control the Device Lock function.
Additional Local I/O Functions 8.
Additional Local I/O Functions 8.4 Watchdog Timer The VP 110/01x board includes a hardware Watchdog timer which can be used by the operating software to monitor the normal operation of the system. The timer is enabled by a board switch (see Figure 8-1) and controlled by software. Once enabled it must be restarted at regular intervals. If it is not restarted for a period of approximately 1 second, the timer will expire and cause a Non-Maskable Interrupt or reset to the local processor. See Section 8.4.
Additional Local I/O Functions 8.4.1 Watchdog Status & Control Register (I/O address 214h) 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | RFU SYSTEM S/W ENABLE STATUS NMI PAT PAT RESET ENABLE LINK RESET 1 2 ENABLE Bits 1- 0: Watchdog Restart Bits (Read/Write) Refer to the following description on watchdog configuration. Bit 2: Select Watchdog Action (Read/Write) This bit selects the following actions when the watchdog times out.
Additional Local I/O Functions 8.4.2 Watchdog Configuration The watchdog circuitry contains features to safeguard against accidental use through faulty or unintended software actions. To enable the watchdog the following sequence of events needs to be performed. 1) Read the watchdog register. Check the status of the watchdog enable jumper (bit 4). If it reads ‘low’ then proceed to step 2. If it reads ‘high’ then the watchdog cannot be enabled in software.
Additional Local I/O Functions 8.4.4 Programming the Watchdog The following functions show how to use the watchdog facility available through the Status and Control registers.
Additional Local I/O Functions bTemp = inbyte (WATCHDOG_STATCTL); bTemp &= ~WD_ACTION_MASK; bTemp |= WD_ACTION_NMI; /* set watchdog action to NMI */ bTemp &= ~WD_SW_ENABLE; /* software disable the watchdog */ outbyte (WATCHDOG_STATCTL, bTemp | WD_PAT_1); outbyte (WATCHDOG_STATCTL, bTemp | WD_PAT_2); outbyte (WATCHDOG_STATCTL, bTemp | WD_PAT_1); /* set and pat twice */ } /* vDisableWatchdog () */ /***************************************************************************** * vPatWatchdog: restart the
Additional Local I/O Functions 8.
Additional Local I/O Functions 8.6 Memory Page and Status Register (I/O address 216h) 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | FLASH MEMORY PAGE 5 PAGE 4 PAGE 3 PAGE 2 PAGE 1 PAGE 0 PROG/EN SELECT STATUS Bits 5 - 0: Application Flash and SRAM page select (read/write) NOTE The Flash devices used are 128 Mbits (16 Mbytes), using page bits 0 to 4.
Additional Local I/O Functions 8.7 Status & Control Register 3 (I/O address 217h) 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | MODE VME GAP VID4 VID3 VID2 VID1 VID0 JUMPER SYSTEM RESET ENABLE Bits 4 - 0: VME64x slot number (Read Only) These bits indicate the state of the VME Geographic Address pins (GA4-GA0) of the VME P1 connector. They will read as ‘1’ if the board is installed in a backplane which does not support these signals.
Additional Local I/O Functions 8.8 Long Duration Timer/Periodic Interrupt Timer The Long Duration Timer (LDT) consists of a 32-bit free running counter with a 32-bit holding register and a Status & Control register. The counter bytes are laid out in little-endian format to permit multi-byte read/write operations. The Status & Control register controls the operation of the LDT. A 32-bit holding register is provided to ensure stable count values are read.
Additional Local I/O Functions 8.8.1 Long Duration Timer/Periodic Interrupt Timer Low Byte 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0 Bits 7 - 0: Low Byte of LDT/PIT (Read/Write) Reading this register causes the current value of the LDT to be transferred to a holding register. This allows a stable 4-byte count to be read. The low byte of the holding register is returned by the read.
Additional Local I/O Functions 8.8.5 LDT/PIT Status & Control Register 7 6 5 4 3 2 1 0 |________|________|_________|________|_________|_________|_________|_________| | | | | | | | | RFU RFU CLOCK INTERRUPT MODE MODE MODE RUN SELECT FLAG 2 1 0 Bit 0: LDT/PIT Run (Read/Write) This bit controls whether the LDT/PIT runs or is stopped.
Additional Local I/O Functions 8.8.6 Programming the LDT/PIT The following code fragments illustrate how the system software, by using the on-board hardware, can create accurate time delays and measure elapsed times, accurate to 1µs, irrespective of the CPU’s operating frequency.
Additional Local I/O Functions It is possible to implement delays of 5ms, 2ms, 1ms, 500µs, 200µs and 100µs by utilizing other PIT modes. The PIT can generate an interrupt whenever the PIT rolls over. The system programmer must initialize the interrupt vector, enable PIC interrupts, etc. The following code fragment shows the basic interrupt handling function.
Additional Local I/O Functions outbyte (CONTROL_STATUS, MODE_STOP); dElapsedTime = (UINT32) inbyte (TIMER_BYTE_0); dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_1)) dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_2)) dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_3)) printf ("Elapsed time = %u.
Additional Local I/O Functions 8.9 Port 80 A header has been provided for monitoring data written to I/O Port 80. The PC BIOS writes status bytes to Port 80 that indicate a boot progress status and/or highlight any faults found. Data written to this port can be monitored using a Logic State Analyzer (LSA) or seven segment hexadecimal displays. See Section A.5.11 for details of the connector used for this port.
PC BIOS The VP 110/01x board is fitted with PC BIOS firmware that performs many of the functions of a standard desktop PC. It also includes additional features specifically tailored for the VME bus environment. In addition to the core BIOS firmware, the board is fitted with BIOS Extensions for remote bootload capability via either of the on-board Ethernet channels. To improve the flexibility of the board, some of these features may be selectively enabled or disabled by an operator using BIOS setup menus.
PC BIOS this switch. A VT100-compatible serial terminal or emulator program should be used. By default the serial line is programmed to operate at 9600 Baud with 8 data bits, 1 stop bit and no parity (8N1). There is no flow control. For fast terminals, the baud rate can be increased via the Serial Console Baud Rate field of the Main Setup menu.
PC BIOS 9.2 The PC BIOS Startup Sequence When the board starts up without operator intervention, it will run a basic Power-On Self-Test (POST) sequence, including ECC DRAM initialization and a DRAM test. The full DRAM test will be omitted on subsequent restarts if the BIOS configuration settings have not been changed. Once the DRAM test has completed, the board will try to bootload application software from any attached mass storage medium or through one or both of the Ethernet interfaces.
PC BIOS 9.3 Boot device selection The order in which the PC BIOS searches for a bootable medium is pre-configured but may be altered by the operator using the Boot setup menu. When the order is changed using this menu it will be retained in non-volatile memory so that the order is maintained after a restart. It is also possible to specify a one-time override of the boot device when the board starts, by pressing the key. This will result in a pop-up menu appearing.
PC BIOS 9.4 PCI Bus Resource Management The local bus structure of the VP 110/01x is quite complex, and is based around two independent PCI busses. In some cases the user may need to understand this structure and in particular how the PC BIOS firmware allocates addresses and interrupt signals to the available hardware resources. The following sections outline this allocation process and provide further details of the PCI bus configuration.
PC BIOS Table 9-1 lists the configurable interrupts for this board. The actual allocation of PCI bus interrupts to available interrupt controller inputs will depend on both the default “Plug-and-play” settings programmed by the PC BIOS, and the way in which the user has overridden them using the Setup screens. When more than one PCI bus interrupt is routed to the same interrupt controller input, that input will remain active while any of the sources connected to it are active.
PC BIOS 9.4.2 PCI Device IDs Each PCI bus, and each device on an individual PCI bus, has a unique ID. For the VP 110/01x, the bus and device IDs are listed in Table 9-2. The ServerWorks chipset includes two PCI bus bridges to interface to the 64-bit and 32-bit on-board PCI busses, and these bridges are identified by the same PCI device ID but with different function codes.
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VME System Architecture Test Handler 10.1 Introduction The VME System Architecture (VSA) Test Handler firmware provides an environment where interactive testing may be performed on one or more Concurrent Technologies’ VME CPU boards. The level of testing provided by VSA is more comprehensive than that provided by the BIOS POST, and testing can also be looped to aid diagnosis of intermittent faults. Failing tests provide diagnostic information that can be used to identify the cause of the problem.
VME System Architecture Test Handler 10.2.3 Starting the Master Test Handler VSA mode is selected by setting the Mode switch to the VSA position as indicated in Figure 9-1. The board will enter VSA mode before the BIOS starts displaying sign-on text, so the first console output will be the VSA user attention prompt. When VSA starts, it outputs attention characters to all possible console devices simultaneously; i.e. a video adapter and the COM1 port.
VME System Architecture Test Handler 10.2.6 BIST Execution BIST execution is started using the TEST command. While a test is executing, no further commands may be entered. It is possible to specify more than one BIST for execution using the “;” separator, for example: T14;T15;T20,4 Execute Test 14, Test 15 and Test 20. Test 20 has a command parameter. BISTs may be executed more than once, automatically, using the iteration count.
VME System Architecture Test Handler 10.3 MTH Command Reference This section details all of the commands available from the MTH (Master Test Handler) prompt. Commands are divided into General and Utility sections. The list below shows the commands in uppercase letters only, but lowercase letters may also be used. Where numbers are entered decimal notation is assumed unless the value ends in ‘H’ or ‘h’ In this case the value is assumed to use hexadecimal notation. 10.3.
VME System Architecture Test Handler SUM [No short command] Prints the pass and fail counts for all BISTs available on the default slot. SUM # # [No short command] - test number, in the range 0-255 Prints the pass and fail count, for the BIST indicated, on the default slot. TEST # [Short command T] # - test number, in the range 0-255 Starts BIST execution on the default slot. The test is run without parameters.
VME System Architecture Test Handler 10.3.3 Utility Commands IRO, IRR, ICR, ICW These commands are reserved for factory testing. They report and modify the state of the VSA board communication data structures.
VSA Mode Diagnostics This chapter describes the board’s initialization into VSA mode and the Tests that can be run from VSA mode. For details of the VSA command line interface, refer to Chapter 10. Some of these tests are described to be run when the board is fitted with additional test hardware at the factory, or in conjunction with other boards. When these tests are run by the user, they may fail simply because this additional hardware is not available.
VSA Mode Diagnostics 11.2 BIST Descriptions The following is a list of the tests that are available in the firmware set installed on this board, together with an overview of the function of each test. A description of each possible error condition, with its code, is given for each test. 11.2.1 Test 1: Test Initialization Routine This pseudo-test performs no actual testing of the board. It sets up in RAM several data values, such as RAM size, that are used by later tests.
VSA Mode Diagnostics 11.2.4 Test 6: Interconnect Image Check This BIST reads and verifies the vendor ID and the board name from the Header Record of the local Interconnect Template. The interconnect template is a data structure used by VSA to communicate between boards. Error codes: 0300h - Image check failed 11.2.5 Test 7: Off-board Interconnect Access This BIST searches for a known interconnect record in the interconnect template of the System Controller board.
VSA Mode Diagnostics 11.2.8 Test 12: Local RAM Fixed Pattern Test This BIST performs a short test on local RAM. The range of memory to be tested depends upon the test handler from which the BIST was invoked. When the test is executed from the power-up test handler, it is necessary to limit execution time; therefore the test range is limited to the block of RAM before the video memory hole, i.e. 30000H to 9FFFFH. When the test is executed from the slave test handler, e.g.
VSA Mode Diagnostics 11.2.11 Test 20: Universe NMI Test This BIST checks the ability of the universe to generate a NMI to the processor using the software generated interrupt via LINT1. Error codes: 0406h - no interrupt generated or spurious interrupt 11.2.12 Test 22: RAM Data and Address Bus Test This BIST checks RAMs data and address bus. First part of the BIST checks data bus wiring for each memory row in specified memory range. It tests each bit of data bus with walking ones and zeros.
VSA Mode Diagnostics 11.2.14 Test 25: Local RAM Dual Address Test This BIST checks for Dual Addressing in the RAM. The range of memory to be tested depends upon the test handler from which the BIST was invoked. When the test is executed from the slave test handler, e.g. during soak testing, the test range is limited to 64 Mbytes; however, each time the BIST is executed it tests a different block.
VSA Mode Diagnostics 11.2.16 Test 28: SCC Interrupt Test This BIST checks that the serial channel on the board is capable of generating an interrupt. A null character is transmitted on the channel to generate a transmit interrupt from that channel. If the interrupt occurs, checks are made to ensure that there is a transmit interrupt pending on the serial device. A channel specific interrupt is generated.
VSA Mode Diagnostics 11.2.20 Test 34: Universe PCI Config Utility This pseudo test configures a Universe PCI slave image register for off-board VME accesses. The following parameters are required: Slave to program (Default = 3), Lower Address (Default = 90000000h), Upper Address (Default = 91000000h), Translation Offset (Default = 0), Control Register Value (Default = 80820000h). This test does not fail. 11.2.
VSA Mode Diagnostics 11.2.23 Test 37: Bus Error Detection Test This BIST checks the operation of the VME Bus Error Detection facilities available on the VP 100/01x board. This BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, all sub-tests are performed. The available sub-tests are listed below, a (D) against the test indicates that it is executed by default when no parameters are supplied.
VSA Mode Diagnostics 11.2.24 Test 39: Watchdog Test This BIST checks the watchdog facilities available on the VP 110/01x board. The BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, a default series of sub-tests is performed. The available sub-tests are listed below, a (D) against the test indicates that it is executed by default when no parameters are supplied.
VSA Mode Diagnostics 11.2.25 Test 40: LDT and PIT Test This BIST checks the operation of the LDT (Long Duration Timer) and the PIT (Periodic Interrupt Timer) facilities available on the VP 110/01x board. This BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, all sub-tests are performed. The available sub-tests are listed below, a (D) against the test indicates that it is executed by default when no parameters are supplied.
VSA Mode Diagnostics 11.2.28 Test 41: StrataFlash Test This BIST checks the programmability of each StrataFlash device on the board. Each sub-test first identifies the device and reports the part number, then an erase/program/verify test is performed for all sectors in the StrataFlash. The original contents of the device are preserved and restored on successful completion. The sub-tests options are: 0 - Test all sectors in all StrataFlash devices. Default test 1 - Test one sector.
VSA Mode Diagnostics 11.2.29 Test 42: Non-Volatile RAM Test This BIST checks the operation of the non-volatile SRAM on the VP 110/01x board. The BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, a default series of sub-tests is performed. The available sub-tests are listed below, a (D) against the test indicates that it is executed by default when no parameters are supplied.
VSA Mode Diagnostics 11.2.30 Test 56: IDE Controller Test This BIST checks the operation of the embedded IDE controller that forms part of the CSB5 south bridge. This test consists of a number of sub-tests, which can be selected via a command line parameter. If the BIST is invoked without parameters, only those tests that exercise the controller are performed.
VSA Mode Diagnostics 11.2.31 Test 58: IDE Fixture Test This BIST checks the operation of the on-board IDE controller by means of an external test fixture. This fixture is identified as “TF0169”. There are no sub-commands or parameters relevant to this test.
VSA Mode Diagnostics 11.2.32 Test 63: PS/2 Mouse Test This BIST tests the PS/2 port and PS/2 mouse (if connected). The PS/2 port test includes opening the auxiliary port on keyboard controller, sending an echo to the auxiliary port and testing the auxiliary bus. The PS/2 mouse test resets the mouse, reads the device identity and echo from the PS/2 mouse and tests the mouse buttons and movement. The sub-test can be selected by command line parameter.
VSA Mode Diagnostics 11.2.33 Test 64: PC Keyboard Test This BIST performs checks on the keyboard controller, the test also determines whether a keyboard is present. First, the keyboard controller’s output buffer is flushed and a ‘keyboard present’ test is performed. The keyboard controller is then enabled and initialized and if successful, the keyboard controller’s self test and interface test are performed. Finally a keyboard interrupt is generated and verified.
VSA Mode Diagnostics 11.2.34 Test 68: Real Time Clock Test This BIST tests the PC compatible, real time clock. The BIST provides a number of sub-tests, which are selected by a command parameter. If no parameter is supplied the current time and date is displayed, the interrupt signal is tested and the non-destructive NVRAM test performed. The sub-tests options are: 0 - Set date and time. Followed by: Hour (0 - 23), Minute (0 - 59), Day (1 - 31), Month (1 - 12), Year (0 - 99).
VSA Mode Diagnostics 11.2.35 Test 69: 82559ER Test This BIST tests the operation of both 82559ER Ethernet controllers on the baseboard. The BIST is split into a series of sub-tests. By default, only the device checks and internal loopback tests are performed, however the other sub-tests can be selected from the MTH command line using BIST parameters. Each sub-test is described in the following sections. This test can be executed at power-up, and may be invoked thereafter by a Master Test Handler.
VSA Mode Diagnostics 11.2.36 Test 70: Maxim 1617 Thermal Sensor Test This BIST checks the operation of the Maxim 1617 Thermal Sensor. This test consists of a number of sub-tests, which can be selected via a command line parameter. If the BIST is invoked without parameters, only basic diagnostics and CPU over-heat are checked. The CPU over-heat temperature is preset to 95°C.
VSA Mode Diagnostics 11.2.36.4 Change Update Frequency This option allows the user to change the update frequency of the Maxim 1617 Thermal Sensor. All possible options are listed below: Value Update Frequency (Hz) 0 0.0625 1 0.125 2 0.25 3 0.5 4 1 5 2 6 4 7 8 Alarms will only trigger when an update occurs. Should there be a temperature spike between readings it will not trigger an alarm. If this is a problem raise the update frequency to 8Hz.
VSA Mode Diagnostics 11.2.36.5 Full Readout This option reads and displays the data currently available from the Maxim 1617 Thermal Sensor. The display is in the following format. !ALERT mask : 1 S/w standby Conv. rate : 0.0625Hz Chip busy CPU OPEN : 0 CPU SHORT Temp. Amb. : xxx^C Temp. CPU Triggered alarms: *** Ambient High Threshold *** *** Ambient Low Threshold *** *** CPU High Threshold *** *** CPU Low Threshold *** : : : : 0 0 ? xxx^C CPU VCC : ? !ALERT mask Hardware alarm mask.
VSA Mode Diagnostics 11.2.37 Test 71: 82559ER Interface Test This BIST verifies the operation of the external Ethernet interface of both 82559ER controllers, when communicating with a second Ethernet equipped board. The test will only run in conjunction with a Concurrent Technologies Soak Test Master. The test exchanges data packets between two boards. One board is designated ‘master’ by the test controller and will transmit first. The received data is checked against expected results.
VSA Mode Diagnostics 11.2.40 Test 101: Display Memory Utility This BIST allows any area of the target board’s local memory to be examined and displayed by the test master. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master. The parameters are: start address of memory area (default 0), length of memory area in bytes (default 10h), data type (1 for byte, 2 for word, and 4 for dword)(default 1).
VSA Mode Diagnostics 11.2.43 Test 104: I/O Write Utility This BIST allows modification of any I/O register on the target board. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master.
VSA Mode Diagnostics 11.2.46 Test 107: Cache Control Utility This BIST allows the status of DRAM and EPROM caching on the target board to be interrogated or configured. If the utility is invoked without parameters, the default action is to display the state of DRAM and EPROM caching. The available options are: 1) disable DRAM caching, 2) enable DRAM and EPROM caching, 3) toggle DRAM caching state, 4) report DRAM and EPROM caching state (default), 5) disable EPROM caching.
VSA Mode Diagnostics 11.2.48 Test 121: PCI Read Utility This BIST allows PCI configuration registers to be examined on the target board. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master.
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Specifications A.1 Functional Specification Processor: • 800MHz or 1.2GHz Pentium III-M with 32 Kbyte Level 1 cache. Level 2 Cache: • 512 Kbytes on-die RAM operating at core frequency. Memory: • 512 Kbytes Flash EPROM for PC BIOS using socketed 28SF040 device. • 512 Kbytes Flash EPROM for factory test firmware. • SDRAM 512 Mbytes to 1 Gbyte defined by order number. Processor burst and cache support.
Specifications A.2 Environmental Specification A.2.1 Temperature Range Operating . Storage . . . . . . . . . . . . . . . . 0 to +55ºC @ 400LFM air flow -40 to +70ºC NOTE If the on-board hard disk drive option is fitted, the operating temperature range will be restricted to +5 to +55ºC and the storage temperature range will be restricted to -40 to +65ºC. NOTE If the battery is fitted, the storage temperature range will be restricted to 0 to +70ºC.
Specifications A.
Specifications A.5.1 VME Interface (P1) Pin-outs The VME interface connector P1 consists of a 160-pin connector with pins assigned as follows: Pin No.
Specifications A.5.2 Auxiliary Connector (P2) Pin-outs The auxiliary connection P2 consists of a 160-pin connector. The pin assignments are as shown in Table A-2. Pin No.
Specifications A.5.3 PMC I/O Connector (P0) Pin-outs Some VP 110/01x variants are fitted with a P0 connector. This is a 95-way (5-row x 19-position) IEC 61076-4-101 2mm pitch connector. It carries all 64 I/O signals from PMC Site 2. The pin assignments conform to the P4V0-64 mapping defined in the ANSI/VITA 35-2000 standard and are shown below.
Specifications A.5.4 Keyboard and Mouse Header (LK1) Pin-outs The keyboard and mouse interface signals are routed to a 2 row x 4-way 0.1 inch pitch header, which is located behind the serial port connector. The pin assignments are shown in Table A-4. Connector location and pin orientation is detailed in Figure A-3. Pin 4 Pin 1 Pin 4 Pin 1 Figure A-3 Keyboard and Mouse Header LK1 Polarization Pin No. Signal Name Pin No.
Specifications A.5.5 Serial Interface (J9) Pin-outs The COM1 RS232 serial interfaces use 8-way RJ45 connectors with the following pinouts. 1 2 3 4 5 6 7 8 Figure A-4 Serial Port RJ45 Connector (Front View) Pin No.
Specifications A.5.6 Ethernet Interface (J15 and J16) Pin-outs The Ethernet Interfaces use 8-way RJ45 connectors with the following pin-out: 1 2 3 4 5 6 7 8 Figure A-5 Ethernet RJ-45 Connector (Front View) Pin No. Signal Name 1 2 3 4 5 6 7 8 Transmit (+) Transmit (-) Receive (+) Not used Not used Receive (-) Not used Not used Table A-7 Ethernet RJ-45 Connector Pin-outs NOTE Ethernet channel 0 connects to J16.
Specifications A.5.7 On-Board Mass Storage Option Connector (S1) Pin-outs Pin No. Signal Name Pin No. Signal Name 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 IDE_RST SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 GND SDREQ SDIOW SDIOR SIORDY SDDACK INT15 SDA1 SDA0 SDCS1 ACTIVITY +5V GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 GND SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 +3.
Specifications A.5.8 PMC Site 1 Connectors (J11, J12, J13 and J14) Pin-outs Signal assignments on the PMC connectors for PMC Site 1 are shown in Tables A-9, A-10, A-11 and A12. Pin No. Signal Name Pin No.
Specifications Pin No. Signal Name Pin No. Signal Name 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 +12V GND +3.3V†† RST# +3.3V AD(30) GND AD(24) IDSEL +3.3V AD(18) AD(16) GND TRDY# GND PERR# +3.3V C/BE(1)# AD(14) M66EN AD(08) AD(07) +3.3V PMC-RSVD PMC-RSVD GND ACK64#† GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 GND +3.3V GND GND GND AD(29) AD(26) +3.3V AD(23) AD(20) GND C/BE(2)# IDSEL B +3.
Specifications Pin No. Signal Name Pin No.
Specifications Pin No. Signal Name Pin No.
Specifications A.5.9 PMC Site 2 Connectors (J21, J22, J23 and J24) Pin-outs Signal assignments on the PMC connectors for PMC Site 2 are shown in Tables A-13, A-14, A-15 and A-16. Pin No. Signal Name Pin No.
Specifications Pin No. Signal Name Pin No. Signal Name 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 +12V GND +3.3V†† RST# +3.3V AD(30) GND AD(24) IDSELC +3.3V AD(18) AD(16) GND TRDY# GND PERR# +3.3V C/BE(1)# AD(14) M66EN AD(08) AD(07) +3.3V PMC-RSVD PMC-RSVD GND ACK64#† GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 GND +3.3V GND GND GND AD(29) AD(26) +3.3V AD(23) AD(20) GND C/BE(2)# IDSEL D +3.
Specifications Pin No. Signal Name Pin No.
Specifications Pin No. Signal Name Pin No.
Specifications A.5.10 Processor Debug Port (J1) Pin-outs The processor debug port, which is supported by a number of emulator devices, is accessible via an Intel specified 30-way receptacle connector with the following pin-out. Pin No.
Specifications A.5.11 Port 80 (J3) Pin-outs 1 3 5 7 9 11 13 2 4 6 8 10 12 14 Figure A-6 Port 80 Connector Pin No.
Breakout Modules B.1 Introduction This section details all the available breakout modules available for use with the VP 110/01x. Each breakout module provides a means of connecting interface cables to the rear I/O of the VP 110/01x. An overview of each breakout module is given with a reference to a pin-out table for each of the connectors identified. B.2 Breakout Modules List The following breakout modules are suitable for use with the VP 110/01x:Sales Part No.
Breakout Modules B.3 AD VP2/004-10 The AD VP2/004-10 product is a 3-row P2 breakout board designed for use with the VP 110/01x-1x VME board. It provides two IDC connectors for the PMC I/O signals on P2, and also makes all these signals available via a single 68-way high-density D-type socket. This breakout requires one slot width behind the backplane. B.3.1 Layout Figure B-1 shows the position of connectors and headers. The AD VP2/004-10 requires a minimum of 75mm depth behind the VME backplane.
Breakout Modules B.4 AD VP2/004-20 The AD VP2/004-20 product is a 5-row P2 breakout board designed for use with the VP 110/01x-3x VME board. It provides two IDC connectors for the PMC I/O signals on P2, and also makes all these signals available via a single 68-way high density D-type socket. It also provides IDC connectors for the EIDE and floppy disk interfaces, and provides a USB connector. This breakout requires one slot width behind the backplane. B.4.
Breakout Modules B.5 AD VP2/005-00 The AD VP2/005-00 product is a P0 and 5-row P2 breakout board designed for use with the VP 110/01x-2x VME board. It provides IDC connectors for the PMC I/O signals on P0 and P2 and standard PC connectors for the EIDE, floppy disk and USB interfaces on P2. B.5.1 Layout Figure B-3 shows the position of connectors and headers. The AD VP2/005-00 requires a minimum of 70mm depth behind the VME backplane.
Breakout Modules B.6 Header/Connector Configuration Tables The headers and connectors are designed to enable use of standard P.C. Interface cables wherever possible. Detailed below are the pin-outs of the headers and connectors used on the breakout modules. Pin No. Signal Name Pin No.
Breakout Modules Pin No. Signal Name 1 2 3 4 +5V DATA (-) DATA(+) GND Table B-4 USB Connector Pin-outs Pin No. Signal Name Pin No.
Breakout Modules Pin No. Signal Name Pin No.
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