Hardware manual

a one-byte buffer.
18.3 FIFOs
To understand the differences between dumb and FIFO (First In, First Out queue discipline) first let's examine
what happens when a UART has sent or received a byte. The UART itself can't do anything with the data
passing thru it, it just receives and sends it. For the obsolete dumb UARTS, the CPU gets an interrupt from the
serial device every time a byte has been sent or received. The CPU then moves the received byte out of the
UART's buffer and into memory somewhere, or gives the UART another byte to send. The obsolete 8250 and
16450 UARTs only have a 1 byte buffer. That means, that every time 1 byte is sent or received, the CPU is
interrupted. At low transfer rates, this is OK. But, at high transfer rates, the CPU gets so busy dealing with the
UART, that is doesn't have time to adequately tend to other tasks. In some cases, the CPU does not get around
to servicing the interrupt in time, and the byte is overwritten, because they are coming in so fast. This is called
an "overrun" or "overflow".
FIFO UARTs help solve this problem. The 16550A (or 16550) FIFO chip comes with 16 byte FIFO buffers.
This means that it can receive up to 14 bytes (or send 16 bytes) before it has to interrupt the CPU. Not only
can it wait for more bytes, but the CPU then can transfer all (14 to 16) bytes at a time. This is a significant
advantage over the obsolete UARTs, which only had 1 byte buffers. The CPU receives less interrupts, and is
free to do other things. Data is rarely lost. Note that the interrupt threshold of FIFO buffers (trigger level) may
be set at less than 14. 1, 4 and 8 are other possible choices. As of late 2000 there was no way the Linux user
could set these directly (setserial can't do it). While many PC's only have a 16550 with 16-byte buffers, better
UARTS have even larger buffers.
Note that the interrupt is issued slightly before the buffer gets full (at say a "trigger level" of 14 bytes for a
16-byte buffer). This allows room for a couple more bytes to be received before the interrupt service routine is
able to actually fetch all these bytes. The trigger level may be set to various permitted values by kernel
software. A trigger level of 1 will be almost like an obsolete UART (except that it still has room for 15 more
bytes after it issues the interrupt).
Now consider the case where you're on the Internet. It's just sent you a short webpage of text. All of this came
in thru the serial port. If you had a 16-byte buffer on the serial port which held back characters until it had 14
of them, some of the last several characters on the screen might be missing as the FIFO buffer waited to get
the 14th character. But the 14th character doesn't arrive since you've been sent the entire page (over the phone
line) and there are no more characters to send to you. It could be that these last characters are part of the
HTML formatting, etc. and are not characters to display on the screen but you don't want to lose format either.
There is a "timeout" to prevent the above problem. The "timeout" works like this for the receive UART
buffer: If characters arrive one after another, then an interrupt is issued only when say the 14th character
reaches the buffer. But if a character arrives and the next character doesn't arrive soon thereafter, then an
interrupt is issued anyway. This results in fetching all of the characters in the FIFO buffer, even if only a few
(or only one) are present. There is also "timeout" for the transmit buffer as well.
18.4 Why FIFO Buffers are Small
You may wonder why the FIFO buffers are not larger. After all, memory is cheap and it wouldn't cost much
more to use buffers in the kilo-byte range. The reason is flow control. Flow control stops the flow of data
(bytes) on serial line when necessary. If a stop signal is sent to serial port, then the stop request is handled by
software (even if the flow control is "hardware"). The serial port hardware knows nothing about flow control.
Serial HOWTO
18.2 Two Types of UARTs 69