Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 52 of 83
5.2 Digital Display Interface
The 4
th
generation of Intel Core Microarchitecture (code name Haswell) migrated the Digital
Display Interface block functionality from PCH to Processor chip itself, thus eliminating latency
due to increasing video resolutions and bandwidths, and creating better integration between
graphics processor and display interface.
The PCH can drive up to three independent digital interfaces natively. One DisplayPort and two
HDMI ports. The processor supports:
 Two Digital Display (x4 DDI) interfaces that can be configured as DisplayPort, HDMI. The
DisplayPort can be configured to use 1, 2, or 4 lanes depending on the bandwidth
requirements and link data rate of RBR (1.62 GT/s), HBR (2.97 GT/s), and HBR2 (5.4 GT/s).
When configured as HDMI, the DDIx4 port can support 2.97 GT/s.
 The HDMI interface supports HDMI with 3D, 4K, Deep Color, and x.v. Color. The DisplayPort
interface supports the VESA DisplayPort Standard Version 1, Revision 2 (DP1.2).
 The processor supports High-bandwidth Digital Content Protection (HDCP) for high-definition
content playback over digital interfaces.
 The processor also integrates dedicated a Mini HD audio controller to drive audio on
integrated digital display interfaces, such as HDMI and DisplayPort. The HD audio controller
on the PCH would continue to support down CODECs, and so on. The processor Mini HD audio
controller supports two High-Definition Audio streams simultaneously on any of the three
digital ports.
 The processor supports streaming any 3 independent and simultaneous display combination
of DisplayPort/HDMI monitors. In the case of 3 simultaneous displays, two High Definition
Audio streams over the digital display interfaces are supported.
 Each digital port is capable of driving resolutions up to 3200x2000 at 60 Hz through
DisplayPort and 4096x2304 at 24 Hz using HDMI.
 DisplayPort Aux CH, DDC channel, Panel power sequencing, and HPD are supported through
the PCH.