Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 50 of 83
5 Interfaces
5.1 PCI Express
This section describes the PCI Express interface capabilities of the processor. See the PCI Express
Base Specification for details of PCI Express.
5.1.1 PCI Express Specifications
 The port may negotiate down to narrower widths.
Support for x1 widths for a single PCI Express mode.
 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
 Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface. This also
does not account for packet overhead and link maintenance.
 Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface. This also
does not account for packet overhead and link maintenance.
 PCI Express reference clock is 100-MHz differential clock.
 Power Management Event (PME) functions.
 Dynamic width capability.
Figure 12 – IPC2 PCI Express Interface scheme
Lynx Point
LP PCH
PCI Express
Root Ports
PCIE_4_TX_P/N
PCIE_4_RX_P/N
Port 4
5Gbps
HOST
/ FACE Module interface
PCIE_50_TX_P/N
PCIE_50_RX_P/N
Port 50
5Gbps
Mini PCIe
Half size
PCIE_1/USB3_0_TX_P/N
PCIE_1/USB3_0_RX_P/N
Flexible IO
PCIE_1/USB3_3
PCIE_2/USB3_1_TX_P/N
PCIE_2/USB3_1_RX_P/N
Flexible IO
PCIE_2/USB3_4
PCIE/
USB3
PLX
PCIE Switch
PEX8603
MUX
2:1
PCIE_6/SATA_3_TX_P/N
PCIE_6/SATA_3_RX_P/N
Flexible IO
PCIE_6/SATA_3
PCIE/
SATA
PCIE
Intel GbE PHY
I218
Intel GbE
controller
I211
Mini PCIe / mSATA
Full size
Port 3
5Gbps
Port 52
5Gbps
PCIE_3/SATA_0_TX_P/N
PCIE_3/SATA_0_RX_P/N
PCIE_3_TX_P/N
PCIE_3_RX_P/N
PCIE_52_TX_P/N
PCIE_52_RX_P/N
PCIE_50_TX_P/N
PCIE_50_RX_P/N
SATA_0_TX_P/N
SATA_0_RX_P/N
SATA0