Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 42 of 83
 Host Interface Features
— 64-bit address master support for systems using more than 4GB of physical memory
— Programmable host memory receive buffers (256 Bytes to 16 KB)
— Intelligent interrupt generation features to enhance driver performance
— Descriptor ring management hardware for transmit and receive
— Software controlled reset (resets everything except the configuration space)
— Message Signaled Interrupts
 Performance Features
— Configurable receive and transmit data FIFO, programmable in 1 KB increments
— TCP segmentation capability compatible with Windows NT* 5.x offloading features
— Fragmented UDP checksum offload for packet reassembly
— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP segmentation
offload)
— Split header support to eliminate payload copy from user space to host space
— Receive Side Scaling (RSS) with two hardware receive queues
— Supports 9018 bytes of jumbo packets
— Packet buffer size
— LinkSec offload compliant with 802.3ae specification
— TimeSync offload compliant with 802.1as specification
 Power Management Features
— Magic Packet* wake-up enable with unique MAC address
— ACPI register set and power down functionality supporting D0 and D3 states
— Full wake up support (APM, ACPI)
— MAC power down at Sx, DMoff with and without WoL