Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 39 of 83
4 Peripherals
4.1 Display Interface
Unlike previous Intel Core iX Generation platforms, Haswell ULT display interface resides mostly
within the processor, with a very small functionality in the PCH. The processor houses memory
interface, display planes, pipes and digital display interfaces/ports while PCH has transcoder. The
PCH integrates digital display side band signals AUX CH, DDC bus and Hot-Plug Detect signals even
though digital display interfaces are moved to processor. There are two pairs of AUX CH, DDC
Clock/Data and Hot-Plug Detect Signals on PCH that correspond to digital display interface/ports.
IPC2 design supports up to three native simultaneous independent and concurrent display
configurations.
Note: During boot only two displays are available and can be configured in BIOS. As soon as OS
has been loaded the third display interface becomes available.
Processor and PCH display data path architecture described in Figure 6 and Figure 7.
Figure 6 – Processor Display Architecture