Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 28 of 83
3.6 System Memory
3.6.1 Processor Integrated Memory Controller
Processor’s Integrated Memory Controller (IMC) supports DDR3L protocol with two independent,
64-bit wide channels. The IMC supports one unbuffered non-ECC DDR3L DIMM per-channel; thus,
allowing up to two device ranks per-channel.
Figure 4 – Memory Interface
IPC2 – Memory Interface
Intel 4
th
Gen Core i7/5/3/
Celeron mobile processor
(Haswell ULT)
Dual core 64-bit
i7-4600U; i5-4300U;
i3-4010U; Celeron-2955U
Integrated
Memory
Controller
SO-DIMM 204-pin
Slot A
DDR3L SDRAM
(1.35V operation)
up to 8GB
DDR3L-1333/1600
SO-DIMM 204-pin
Slot B
DDR3L SDRAM
(1.35V operation)
up to 8GB
DDR3L-1333/1600
MEMA_DQS_P/N[7:0]
MEMA_DQ[63:0]
MEMA_ADD[15:0]
MEMA_CLK_P/N[3:0]
MEMA_CLKE[3:0]
MEMA_CS[3:0]/BS[2:0]/ODT[3:0]
MEMA_RAS/CAS/WE
MEMB_DQS_P/N[7:0]
MEMB_DQ[63:0]
MEMB_ADD[15:0]
MEMB_CLK_P/N[3:0]
MEMB_CLKE[3:0]
MEMB_CS[3:0]/BS[2:0]/ODT[3:0]
MEMB_RAS/CAS/WE
Channel A
Channel B
SPD
EEPROM
SPD
EEPROM
SMBus
Controller
SMB_SCL
SMB_SDA