Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 26 of 83
3.5.1 Functional Blocks
Figure 3 – PCH Internal Clock Diagram
The PCH has one main PLL in which its output is divided down through Modulators and Dividers
to provide great flexibility in clock source selection, configuration, and better power management.
Table 15 describes the PLLs on the PCH and the clock domains that are driven from the PLLs.
Table 15 – PCH PLL