Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 23 of 83
3.3.1.9 RTC
The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of battery-
backed RAM. The real-time clock performs two key functions—keeping track of the time of day
and storing system data, even when the system is powered down. The RTC operates on a 32.768
kHz crystal and a 3V battery.
3.3.1.10 GPIO
Various general purpose inputs and outputs are provided for custom system design. Refer to
section 6.4.
3.3.1.11 System Management Bus (SMBus)
The PCH provides System Management Bus (SMBus) 2.0 host controller as well as SMBus Slave
Interface. The host controller provides a mechanism for the processor to initiate communications
with SMBus peripherals (slaves). The PCH is also capable of operating in a mode in which it can
communicate with I
2
C compatible devices. The host SMBus controller supports up to 100 KHz
clock speed.
3.3.1.12 High Definition Audio Controller
The PCH High Definition Audio (HDA) controller communicates with the external codec(s) over
the Intel® High Definition Audio serial link. The controller consists of a set of DMA engines that
are used to move samples of digitally encoded data between system memory and an external
codec(s). The PCH implements four output DMA engines and 4 input DMA engines. The output
DMA engines move digital data from system memory to a D/A converter in a codec. The PCH
implements a single Serial Data Output signal (HDA_SDO) that is connected to external codecs.
The input DMA engines move digital data from the A/D converter in the codec to system memory.
The PCH implements four Serial Digital Input signals (HDA_SDI[1:0]) supporting two audio codecs.
Audio software renders outbound and processes inbound data to/from buffers in system memory.
The location of individual buffers is described by a Buffer Descriptor List (BDL) that is fetched and
processed by the controller. The data in the buffers is arranged in a predefined format. The output
DMA engines fetch the digital data from memory and reformat it based on the programmed
sample rate, bit/sample and number of channels. The data from the output DMA engines is then
combined and serially sent to the external codecs over the Intel High Definition Audio link. The
input DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is then written
to memory in the predefined format for software to process. Each DMA engine moves one stream
of data. A single codec can accept or generate multiple streams of data, one for each A/D or D/A
converter in the codec. Multiple codecs can accept the same output stream processed by a single
DMA engine. Codec commands and responses are also transported to and from the codecs using
DMA engines.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192
kHz, the Intel HD Audio controller provides audio quality that can deliver CE levels of audio
experience. On the input side, the PCH adds support for an array of microphones.