Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 21 of 83
3.3.1.3 Serial ATA (SATA) Controller
The PCH has one integrated SATA host controller that support independent DMA operation on up
to four ports and supports data transfer rates of up to 6 Gbps. The SATA controller contains one
mode of operation – an AHCI mode using memory space. The SATA controller no longer supports
legacy mode using I/O space. Therefore, AHCI software is required. The PCH supports the Serial
ATA Specification, Revision 3.1.
3.3.1.3.1 AHCI
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a standardized
programming interface for SATA host controllers. Platforms supporting AHCI may take advantage
of performance features such as port independent DMA Engines – each device is treated as a
master – and hardware-assisted native command queuing. AHCI also provides usability
enhancements such as Hot-Plug and advanced power management. AHCI requires appropriate
software support (such as an AHCI driver) and for some features, hardware support in the SATA
device or additional platform hardware.
3.3.1.4 Low Pin Count (LPC) Interface
The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count
(LPC) bridge function of the PCH resides in PCI Device 31: Function 0. In addition to the LPC bridge
interface function, D31:F0 contains other functional units including DMA, interrupt controllers,
timers, power management, system management, GPIO, and RTC.
3.3.1.5 Serial Peripheral Interface (SPI)
The SPI Flash Controller supports running instructions at 20 MHz, 33 MHz, and 50 MHz and used
by the PCH for BIOS code, to provide chipset configuration settings, integrated Gigabit Ethernet
MAC/PHY configuration and Intel® Management Engine (Intel® ME) settings. The SPI Flash
Controller supports the Serial Flash Discoverable Parameter (SFDP) JEDEC standard, which
provides a consistent way of describing the functional and feature capabilities of serial flash
devices in a standard set of internal parameter tables. The SPI Flash Controller queries these
parameter tables to discover the attributes to enable divergent features from multiple SPI part
vendors, such as Quad I/O Fast Read capabilities or device storage capacity, among others.
3.3.1.6 Universal Serial Bus (USB) Controllers
The PCH contains one eXtensible Host Controller Interface (xHCI) controller and one Enhanced
Host Controller Interface (EHCI) controller. The xHCI controller supports up to 8 USB 2.0 ports of
which 4 can be configured as SuperSpeed (USB 3.0) ports.
3.3.1.7 Flexible I/O
Flexible I/O is an architecture to allow some high speed signals to be configured as PCIe, USB 3.0
or SATA signals per I/O needs on a platform. Through soft straps, the functionality on these
multiplexed signals are selected to meet the I/O needs on the platform. There are 14 differential
pairs that are split between the three interfaces. Among them, 6 differential pairs are multiplexed:
2 multiplexed differential pairs can be configured to be used as PCIe port 1, 2 or USB3.0 port 3, 4