Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 20 of 83
3.3 PCH (Chipset)
Haswell ULT platform designed in a compact single MCP package that contains both processor
and PCH dies on the same package board. The PCH provides extensive I/O support. Functions and
capabilities include:
 PCI Express* Base Specification, Revision 2.0 support for up to six ports with transfers up
to 5 GT/s
 ACPI Power Management Logic Support, Revision 4.0a
 Enhanced DMA controller, interrupt controller, and timer functions
 Integrated SATA host controllers within dependent DMA operation on up to four ports
 xHCI USB controller provides support for up to 8 USB ports, of which four can be
configured as SuperSpeed USB 3.0 ports
 Flexible I/O allows some high speed I/O signals to be configured as PCIe, SATA or USB 3.0
 Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
 System Management Bus (SMBus), Version 2.0 with additional support for I2C devices
 Supports Intel® High Definition Audio (Intel® HD Audio)
 Supports Intel® Rapid Storage Technology (Intel® RST)
 Supports Intel® Active Management Technology (Intel® AMT)
 Supports Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
 Integrated Clock Controller
 Intel® Flexible Display Interconnect (Intel® FDI)
 Low Pin Count (LPC) interface
 Serial Peripheral Interface (SPI) support
 Two integrated Intel® serial I/O I
2
C Host controllers
 Intel® Anti-Theft Technology (Intel® AT)
3.3.1 PCH Capability Overview
The following sub-sections provide an overview of the PCH capabilities.
3.3.1.1 Direct Media Interface (DMI)
Haswell ULT platform (MCP package) features package internal DMI and not available on external
pins. Direct Media Interface (DMI) is the chip-to-chip connection between the processor and PCH.
This high-speed interface integrates advanced priority-based servicing allowing for concurrent
traffic and true isochronous transfer capabilities.
3.3.1.2 PCI Express* Interface
The PCH provides up to 6 PCI Express Root Ports, supporting the PCI Express Base Specification,
Revision 2.0. Each Root Port x1 lane supports up to 5 Gbps bandwidth in each direction (10 Gbps
concurrent). Refer to section 5.1 for detailed feature set.