Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 18 of 83
3.1.3.1 System States
Table 10 – System States
State
Description
G0/S0
Full On Mode, Display On
G1/S3-Cold
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not
supported by the processor).
G1/S4
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5
Soft off. All power lost (except wakeup on PCH). Total reboot.
G3
Mechanical off. All power removed from system.
Table 11 – Processor Core States
State
Description
C0
Active mode, processor executing code.
C1
Auto HALT state.
C1E
Auto HALT state with lowest frequency and voltage operating point.
C3
Execution cores in C3 state flush their L1 instruction cache, L1 data cache,
and L2 cache to the L3 shared cache. Clocks are shut off to each core.
C6
Execution cores in this state save their architectural state before removing
core voltage.
C7
Execution cores in this state behave similarly to the C6 state. If all execution
cores request C7 state, L3 cache ways are flushed until it is cleared. If the
entire L3 cache is flushed, voltage will be removed from the L3 cache. Power
removal to SA, Cores and L3 will reduce power consumption.
C8
C7 state plus voltage is removed from all power domains after required state
is saved. PLL is powered down.
C9
C8 state plus processor V
CC
input voltage at 0 V.
C10
C9 state plus VR12.6 is set to low-power state, near shut off.
While executing code, Enhanced Intel SpeedStep® Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating point is
defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle
state is defined by ACPI as a C-state. In general, deeper power C-states have longer entry and exit
latencies.