Specifications

CompuLab Ltd. IPC2 – Hardware Specification Page 16 of 83
3 Platform
3.1 Processor
The 4
th
Generation Intel® Core™ processor based on Mobile U-Processor line are 64-bit, multi-
core processors built on 22-nanometer process technology. Haswell ULT processor designed for a
two-chip platform on a single Multi-Chip Package (MCP) that includes a processor die and low-
power Platform Controller Hub (PCH) die, and enables higher performance and lower power
consumption relatively to previous generation. The processor includes Integrated Display Engine,
Processor Graphics, and an Integrated Memory Controller. The processor is designed for mobile
platforms.
3.1.1 Processor Features
 Two execution cores
 A 32-KB instruction and 32-KB data first-level cache (L1) for each core
 A 512-KB shared instruction / data second-level cache (L2), shared among all cores
 Up to 4-MB shared instruction / data third-level cache (L3), shared among all cores
3.1.2 Supported Technologies
 Intel® Virtualization Technology (Intel® VT)
 Intel® Active Management Technology 9.5 (Intel® AMT9.5)
 Intel® Trusted Execution Technology (Intel® TXT)
 Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
 Intel® Hyper-Threading Technology (Intel® HT Technology)
 Intel® 64 Architecture
 Execute Disable Bit
 Intel® Turbo Boost Technology 2.0
 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
 Intel® Secure Key
 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSXNI)