Specifications

ManualsBrandsCompuLab ManualsComputer equipmentIPC2

CompuLab Ltd. Revision 1.2 September 2014

IPC2

Hardware Specification

Summary of content (83 pages)

PAGE 1
IPC2 Hardware Specification CompuLab Ltd. Revision 1.
PAGE 2
Legal Notice © 2013 CompuLab Ltd. All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise without the prior written permission of CompuLab Ltd. No warranty of accuracy is given concerning the contents of the information contained in this publication.
PAGE 3
Revision History Revision 1.0 1.1 1.2 1.3 CompuLab Ltd. HW Engineer Maxim Birger Maxim Birger Maxim Birger Maxim Birger Revision Changes Initial public release Typo fixes and diagram updates Fixed RS232 serial COM port mapping Added power supply temperature ratings: 10.
PAGE 4
Table of Contents Legal Notice................................................................................................................................................... 2 Revision History ............................................................................................................................................ 3 1 2 3 Introduction ........................................................................................................................................ 10 1.
PAGE 5
3.3.1.10 GPIO .................................................................................................................................... 23 3.3.1.11 System Management Bus (SMBus) ..................................................................................... 23 3.3.1.12 High Definition Audio Controller......................................................................................... 23 3.4 Intel Management Engine..................................................................
PAGE 6
4.6 5 Interfaces ............................................................................................................................................ 50 5.1 7 PCI Express .................................................................................................................................. 50 5.1.1 PCI Express Specifications ....................................................................................................... 50 5.1.2 Mini PCI Express* Edge Connector .............
PAGE 7
.3 8 Intel Virtualization Technology ................................................................................................... 71 Power Management ........................................................................................................................... 73 8.1 9 Embedded Controller Renesas H8S/2113 ................................................................................... 73 Electrical Characteristics .................................................................
PAGE 8
Figure 17 – IPC2 Mini PCIe/mSATA scheme .............................................................................................. 63 Figure 18 – FACE Module concept ............................................................................................................. 65 Figure 19 – FACE Module FM-USB3 block diagram ................................................................................... 69 Figure 20 – FM-USB3 PCB Assembly Top ...........................................................
PAGE 9
Table 26 – LAN ports LEDs status notification ........................................................................................... 43 Table 27 – Wireless Module Features ....................................................................................................... 44 Table 28 – mini PCI Express edge connector pinout ................................................................................. 51 Table 29 – Downstream Port HDMI Connector Pinout ............................................
PAGE 10
1 Introduction 1.1 About This Document This document is part of a set of reference documents providing information necessary to operate Compulab’s IPC2 computer. 1.2 Reference For additional information not covered in this manual, please refer to the documents listed in Table 1. Table 1 – Reference Documents Document Ordering Information Guide Location http://fit-pc.com/download/General/orderinginformation-guide.pdf Application Note - fit-PC products http://fit-pc.
PAGE 11
1.3 Terms and Acronyms Table 2 – Terms and Acronyms Term APM B2B BER bps BT CAN Codec DDR DSP FACE Module FM-xxxx GB/s GPIO GT/s HW JTAG kbps LAN MB/s Mbps MT/s NVM OTP PCH PCM PEG Rx SCH SDRAM SIM SoC SPI Tx UART USB USB-OTG USIM VCTCXO WLAN XO CompuLab Ltd.
PAGE 12
2 System Overview 2.1 Highlights IPC2 is a fully functional miniature computer based on Intel 4th generation (Haswell ULT) Mobile Intel® Core™ 64-bit dual core processor family. Together with powerful Intel HD graphics engine, rich peripherals and connectivity options, completely fanless design delivers outstanding performance at lowest power consumption of any PC at its class.
PAGE 13
Table 4 – Display and Graphics Specifications Feature GPU Video Output 1 Video Output 2 Video Output 3 Specifications Intel HD Graphics 4400 Triple display mode supported HDMI 1.4a up to 4096 x 2304 @ 24Hz DisplayPort 1.2 up to 3200 x 2000 @ 60Hz HDMI 1.4a up to 4096 x 2304 @ 24Hz Table 5 – Audio Specifications Feature Codec Audio Output Audio Input Specifications Realtek ALC888-VC2 HD audio codec Analog stereo output Digital 7.1+2 channels S/PDIF output 3.
PAGE 14
Table 8 – Mechanical and Environmental Specifications Feature Input Voltage Power Consumption Operating Temperatures Enclosure Material Cooling Dimensions Weight Specifications Unregulated 10 – 15VDC input (Note 6) 6W – 24W 1. Commercial HDD models: 0°C – 50°C SSD models: 0°C – 70°C 2. Extended (TE) SSD models only: -20°C – 70°C 3. Industrial (TI) SSD models only: -40°C – 70°C Die Cast Aluminum Passive Cooling Fanless Design 19cm x 16cm x 4cm 1150gr Notes: 1.
PAGE 15
2.3 System Block Diagram IPC2 system Top Level Block Diagram is shown below. Later chapters in this document describe functions and entities shown in the below diagram. Figure 1 – IPC2 Top Level Block Diagram DDR3L SDRAM (up to 8GB DDR3L-1600) SO-DIMM 204-pin slot A MEM Channel A (x64, 800MHz max) DDR3L SDRAM (up to 8GB DDR3L-1600) SO-DIMM 204-pin slot B MEM Channel B (x64, 800MHz max) Memory Controller HDMI 1.4a HDMI port HDMI 1.
PAGE 16
3 Platform 3.1 Processor The 4th Generation Intel® Core™ processor based on Mobile U-Processor line are 64-bit, multicore processors built on 22-nanometer process technology. Haswell ULT processor designed for a two-chip platform on a single Multi-Chip Package (MCP) that includes a processor die and lowpower Platform Controller Hub (PCH) die, and enables higher performance and lower power consumption relatively to previous generation.
PAGE 17
3.1.3 Processor Power States This chapter provides information on the processor Advanced Configuration and Power Interface (ACPI) states. Figure 2 – Processor Power States CompuLab Ltd.
PAGE 18
3.1.3.1 System States Table 10 – System States State G0/S0 G1/S3-Cold G1/S4 G2/S5 G3 Description Full On Mode, Display On Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the processor). Suspend-to-Disk (STD). All power lost (except wakeup on PCH). Soft off. All power lost (except wakeup on PCH). Total reboot. Mechanical off. All power removed from system.
PAGE 19
3.2 Processor Graphics Controller New Graphics Engine Architecture includes 3D compute elements, Multi-format hardware assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high definition playback, video quality, and improved 3D performance and Media. The Display Engine handles delivering the pixels to the screen. GSA (Graphics in System Agent) is the primary channel interface for display memory accesses and “PCI-like” traffic in and out. 3.2.
PAGE 20
3.3 PCH (Chipset) Haswell ULT platform designed in a compact single MCP package that contains both processor and PCH dies on the same package board. The PCH provides extensive I/O support. Functions and capabilities include:                   PCI Express* Base Specification, Revision 2.0 support for up to six ports with transfers up to 5 GT/s ACPI Power Management Logic Support, Revision 4.
PAGE 21
3.3.1.3 Serial ATA (SATA) Controller The PCH has one integrated SATA host controller that support independent DMA operation on up to four ports and supports data transfer rates of up to 6 Gbps. The SATA controller contains one mode of operation – an AHCI mode using memory space. The SATA controller no longer supports legacy mode using I/O space. Therefore, AHCI software is required. The PCH supports the Serial ATA Specification, Revision 3.1. 3.3.1.3.
PAGE 22
and the other 4 differential pairs can be configured to be used as PCIe port 6 lane 3 to 0 or SATA port 3 to 0. The below example illustrates how the signals are utilized for Flexible I/O. Table 12 – Flexible I/O High Speed Signal settings with PCIe, USB3.0, and SATA Ports CONFIG 1 CONFIG 2 (default) 2x PCIe2.0 2x USB3.0 CONFIG 3 CONFIG 4 CONFIG 5 3x PCIe2.0 1x SATA3.0* 1x PCIe2.0 1x SATA3.0* 2x USB3.0 2x SATA3.0* 2x USB2.0 2x PCIe2.0 1x SATA3.0* 1x USB3.0 2x SATA3.0* 2x USB2.0 1x PCIe2.0 3x SATA3.
PAGE 23
3.3.1.9 RTC The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of batterybacked RAM. The real-time clock performs two key functions—keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 kHz crystal and a 3V battery. 3.3.1.10 GPIO Various general purpose inputs and outputs are provided for custom system design. Refer to section 6.4. 3.3.1.
PAGE 24
3.4 Intel Management Engine This embedded operating environment is called the Intel Management Engine (Intel ME).
PAGE 25
3.5 System Clocks The PCH provides a complete system clocking solution through Integrated Clocking. PCH based platforms require several single-ended and differential clocks to synchronize signal operation and data propagation system-wide between interfaces and across clock domains. In Integrated Clock mode, all the system clocks will be provided by PCH from a 24 MHz crystal generated clock input. The output signals from PCH are:    6x 100 MHz differential sources for PCI Express* 2.
PAGE 26
3.5.1 Functional Blocks Figure 3 – PCH Internal Clock Diagram The PCH has one main PLL in which its output is divided down through Modulators and Dividers to provide great flexibility in clock source selection, configuration, and better power management. Table 15 describes the PLLs on the PCH and the clock domains that are driven from the PLLs. Table 15 – PCH PLL CompuLab Ltd.
PAGE 27
Table 16 provides a basic description of the available spread modulators. The spread modulators each operate on the XCK PLL’s 2.7 GHz outputs. Spread Spectrum tuning and adjustment can be made on the fly without a platform reboot using specific programming sequence to the clock registers. Table 16 – Modulator Block 3.5.2 Clock Configuration Access Overview The PCH provides increased flexibility of host equivalent configurability of clocks, using Intel ME FW.
PAGE 28
3.6 System Memory 3.6.1 Processor Integrated Memory Controller Processor’s Integrated Memory Controller (IMC) supports DDR3L protocol with two independent, 64-bit wide channels. The IMC supports one unbuffered non-ECC DDR3L DIMM per-channel; thus, allowing up to two device ranks per-channel. Figure 4 – Memory Interface IPC2 – Memory Interface MEMA_DQS_P/N[7:0] MEMA_CLK_P/N[3:0] SMB_SCL SMB_SDA SO-DIMM 204-pin Slot A DDR3L SDRAM (1.
PAGE 29
3.6.2 System Supported Memory            Two channels of DDR3L SDRAM memory with unbuffered Small Outline Dual In-Line Memory 204-pin Modules (SO-DIMM) Up to 16GB (2x 8GB) DDR3L-1333/1600 Single-channel and dual-channel memory organization modes Data burst length of eight for all memory organization modes System Memory Interface I/O Voltage of 1.35 V only DDR3L SDRAM SO-DIMMs running at 1.
PAGE 30
Table 18 – Supported Max Memory Size per SO-DIMM 3.6.3 System Memory Timing Support The IMC supports the following Speed Bins, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:      tCL = CAS Latency tRCD = Activate Command to READ or WRITE Command delay tRP = PRECHARGE Command Period CWL = CAS Write Latency Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks.
PAGE 31
3.6.4 System Memory Organization Modes The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the SO-DIMM Modules are populated in each memory channel, a number of different configurations can exist. 3.6.4.1 Single-Channel Mode In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B SO-DIMM connectors are populated in any order, but not both. 3.6.4.
PAGE 32
3.7 Storage IPC2 supports various types of storage devices due to advanced PCH SATA Host Controller capabilities and I/O availability, described in section 3.3.1.3. Supported devices include HDD and SSD storage devices in 2.5’’ form factor. HDD limited to 5400rpm only due to power dissipation reasons. mSATA NAND Flash solid state drive modules supported as well and share mini PCIe full size slot. For detailed architecture refer to section 6.1.
PAGE 33
3.7.1 Certified storage devices 3.7.1.1 HDD examples Table 20 – WD Scorpio Blue HDD series CompuLab Ltd.
PAGE 34
Table 21 – WD Scorpio Blue HDD series (cont.) CompuLab Ltd.
PAGE 35
Table 22 – Hitachi CinemaStar C5K750 HDD models CompuLab Ltd.
PAGE 36
Table 23 – Seagate Momentus HDD series CompuLab Ltd.
PAGE 37
3.7.1.2 mSATA SSD examples Table 24 – Micron mSATA NAND Flash SSD CompuLab Ltd.
PAGE 38
Table 25 – ACPI CMS2G-M SSD CompuLab Ltd.
PAGE 39
4 Peripherals 4.1 Display Interface Unlike previous Intel Core iX Generation platforms, Haswell ULT display interface resides mostly within the processor, with a very small functionality in the PCH. The processor houses memory interface, display planes, pipes and digital display interfaces/ports while PCH has transcoder. The PCH integrates digital display side band signals AUX CH, DDC bus and Hot-Plug Detect signals even though digital display interfaces are moved to processor.
PAGE 40
Figure 7 – PCH Display Architecture Display is the presentation stage of graphics. This involves:        CompuLab Ltd.
PAGE 41
4.2 Network The following section provides information about IPC2 main network components and features. 4.2.1 LAN1 – Intel MAC/PHY GbE Controller The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel I218 Platform LAN PHY device.
PAGE 42
 Host Interface Features — 64-bit address master support for systems using more than 4GB of physical memory — Programmable host memory receive buffers (256 Bytes to 16 KB) — Intelligent interrupt generation features to enhance driver performance — Descriptor ring management hardware for transmit and receive — Software controlled reset (resets everything except the configuration space) — Message Signaled Interrupts  Performance Features — Configurable receive and transmit data FIFO, programmable in 1 KB
PAGE 43
4.2.2 LAN2 – Intel I211AT GbE Controller Intel Ethernet I211 controller is a single port, compact, low power component that supports GbE designs. The I211 offers a fully-integrated GbE Media Access Control (MAC), Physical Layer (PHY) port and supports PCI Express 2.1 (5GT/s). The I211 enables 1000BASE-T implementations using an integrated PHY. It can be used for server system configurations such as rack mounted or pedestal servers, in an add-on NIC or LAN on Motherboard (LOM) design.
PAGE 44
4.3 Wireless Networks IPC2 configured with Intel 7260HMW module in mini PCIe half size form factor. The 7260HMW is highly integrated 2.4/5GHz dual band IEEE 802.11ac and Bluetooth 4.0 in a single Intel 7260 chip with two host interfaces, PCI Express Host interface used for communication with WLAN part of a baseband chip and USB Host interface used for communication with BT part of a baseband chip, thus allowing higher and more effective data management and throughput.
PAGE 45
Figure 8 – Wireless Module Block Diagram Figure 9 – Wireless Module Mechanical Dimensions CompuLab Ltd.
PAGE 46
4.5 Audio IPC2 system support analog and digital inputs/outputs via standard 3.5’’ audio jacks. For system audio specifications refer to Table 5. 4.5.1 Audio Codec General Description IPC2 incorporates Realtek ALC888S-VC2 audio codec. ALC888S-VC2 is a high-performance 7.1+2 Channel High Definition Audio Codec with two independent S/PDIF outputs. It feature ten DAC channels that simultaneously support 7.
PAGE 47
             Two independent S/PDIF-OUT converters support 16/20/24-bit, 4.1k/48k/88.2k/96k/192kHz sample rate. One converter for normal S/PDIF output, the other outputs an independent digital stream to the HDMI transmitter One S/PDIF-IN converter supports 44.
PAGE 48
Figure 10 – Audio Codec Functional Block Diagram The markers in the Figure 10 apply to audio functionality implemented in IPC2 system and summarized below: 1. 2. 3. 4. 5. Audio Jack Detect function implemented via Sense A: Analog audio output: Port D, FRONT_HOUT_R/L (detect via 5k) Analog audio input: Port B, MIC_IN_R/L (detected via 20k) Digital audio output: S/PDIF-OUT1 Digital audio input: S/PDIF-IN CompuLab Ltd.
PAGE 49
4.6 Super-I/O Controller IPC2 design provides RS232 serial communication between Data Terminal Equipment (Host) and Data Communication Equipment (Device) by the means of Super-I/O Controller SMSC SIO1007, which implements LPC Bus to UART Bridge. The SIO1007 implements the LPC interface with the LPC PortSwitch interface. The LPC PortSwitch interface is a hot switchable external docking LPC interface.
PAGE 50
5 Interfaces 5.1 PCI Express This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. 5.1.1 PCI Express Specifications        The port may negotiate down to narrower widths. Support for x1 widths for a single PCI Express mode. 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported. Gen1 Raw bit-rate on the data pins of 2.
PAGE 51
5.1.2 Mini PCI Express* Edge Connector Table 28 – mini PCI Express edge connector pinout mini PCI Express edge connector Pin # Pin Name Signal Description Pin # 1 WAKE# Open drain, active low signal driven low by a mini PCIe card to reactivate the PCIe link 3 COEX1/Reserved Pin Name Signal Description 2 3.3V 3.3V power rail 4 GND Ground connection COEX2/Reserved Reserved for future wireless coexistence control interface between radios (if needed) 6 1.5V 1.
PAGE 52
5.2 Digital Display Interface The 4th generation of Intel Core Microarchitecture (code name Haswell) migrated the Digital Display Interface block functionality from PCH to Processor chip itself, thus eliminating latency due to increasing video resolutions and bandwidths, and creating better integration between graphics processor and display interface. The PCH can drive up to three independent digital interfaces natively. One DisplayPort and two HDMI ports.
PAGE 53
5.2.1 High Definition Multimedia Interface (HDMI) The High-Definition Multimedia Interface (HDMI) is provided for transmitting uncompressed digital audio and video signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. It can carry high quality multi-channel audio data and all standard and high-definition consumer electronics video formats.
PAGE 54
5.2.1.1 HDMI Connector Table 29 shows the pin assignments of the HDMI external connector on a downstream port on a Source device (IPC2). Table 29 – Downstream Port HDMI Connector Pinout Pin # 1 3 5 7 9 11 13 15 17 19 CompuLab Ltd.
PAGE 55
Table 30 – Downstream Port HDMI Connector Signal Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Signal TMDS_DATA2+ TMDS_DATA2 Shield TMDS_DATA2TMDS_DATA1+ TMDS_DATA1 Shield TMDS_DATA1TMDS_DATA0+ TMDS_DATA0 Shield TMDS_DATA0TMDS_CLK+ TMDS_CLK Shield TMDS_CLKCEC Reserved DDC_SCL DDC_SDA GND PWR_5V HPD Source Direction Out Out Out Out Out Out Out Out In/Out Out In/Out Out In Description Data differential pair 2 - Link 1 Data differential pair 1 - Link 1 Data differential pair 0 - Link
PAGE 56
isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link management and device control. The Hot Plug Detect (HPD) signal serves as an interrupt request for the sink device. The processor is designed in accordance with the VESA DisplayPort Standard Version 1.2a. The processor supports VESA DisplayPort PHY Compliance Test Specification 1.2a and VESA DisplayPort Link Layer Compliance Test Specification 1.2a.
PAGE 57
5.2.3.1 DisplayPort Connector Table 31 shows the pin assignments of the DisplayPort external connector on a downstream port on a Source device (IPC2) and Table 32 show the pin assignments of the DisplayPort external connector on an upstream port on a Sink device (DisplayPort Monitor). Table 31 – Downstream Port DP Connector Pinout Notes: 1. Pins 13 and 14 must be connected to ground through a pull-down device.
PAGE 58
Table 32 – Upstream Port DP Connector Pinout Notes: 1. Pins 13 and 14 must be connected to ground through a pull-down device. External devices and cable assemblies must be designed to not rely on a low impedance ground path from these pins. 2. Pin 20, PWR Out, must provide +3.3 volts ±10% with a maximum current of 500mA and a minimum power capability of 1.5 watts. CompuLab Ltd.
PAGE 59
Table 33 shows the wiring of an external cable connector assembly. Table 33 – Display Port Cable CompuLab Ltd.
PAGE 60
5.3 USB Interface IPC2 platform provides 6 downstream USB interface ports for bus-powered and self-powered devices, four USB3.0 SuperSpeed 5Gbps and two USB2.0 compliant. IPC2 USB interface scheme shown in the following diagram. Figure 15 – IPC2 USB Interface scheme USB2_0_P/N Port 1 USB2.0 USB2_1_P/N Port 1 USB3.0 5Gbps USB3_0_TX_P/N USB3_0_RX_P/N Port 2 USB3.0 5Gbps USB3_1_TX_P/N USB3_1_RX_P/N Port 4 USB2.0 USB2_3_P/N Port 5 USB2.0 USB2_2_P/N USB2 USB3 USB2 EHCI USB2.0 xHCI USB3.
PAGE 61
5.4 RS232 Serial Interface IPC2 design provides three RS232 serial communication ports. COM1/2 support 2-wire interface (Tx/Rx) and COM3 support full RS232 signal set, when COM1 implemented via Embedded Controller UART and COM2/3 by UARTs located in Super-I/O Controller. Due to small dimension physical port is implemented with ultra mini serial connector with the pinout in the table below.
PAGE 62
Table 35 – COM3 Serial Port Pinout Pin # 1 Signal COM3_TX Host Direction Out 2 COM3_RTS Out 3 COM3_RX In 4 COM3_CTS In 5 COM3_DTR Out 6 COM3_DSR In 7 COM3_RI N/A Description Transmit Data – Carries data from DTE to DCE Request To Send – DTE requests the DCE prepare to receive data Receive Data – Carries data from DCE to DTE Clear To Send – Indicates DCE is ready to accept data Data Terminal Ready – Indicates presence of DTE to DCE Data Set Ready – DCE is ready to receive commands or dat
PAGE 63
6 Miscellaneous Features 6.1 Mini PCI Express/mSATA sharing IPC2 advanced platform components and Compulab’s flexible system design offers extremely high utilization of different functionalities and mechanical Form Factors to be implemented on the same HW. Mini PCIe and mSATA share the same slot, and allow the flexibility to install both storage and PCI express devices.
PAGE 64
6.2 SIM Interface IPC2 system incorporates micro SIM slot with dedicated interface to mini PCIe full size slot. In conjunction with cellular modem and authenticated micro SIM card from your mobile operator, the system can be used for cellular communication, data and/or voice (depends on modem). 2G/3G/4G cellular modems in mini PCIe card form factor supported. The micro SIM slot uses 6pin interface. 6.
PAGE 65
6.5 FACE Module Interface FACE Module (Function And Connectivity Extension Module) designed as additional/optional system board providing extended functionality and IO connectivity options. The interface between main system board and FACE module implemented with high speed, low pitch, and high pin count board-to-board connector (B2B). Connector’s pinout including signals mapping and description described later in this chapter.
PAGE 66
6.5.1 Extension Connectors Complete B2B receptacle and plug connector’s specifications shown in the tables below. Table 37 – B2B receptacle connector HOST side Item Manufacturer PN Type Positions Pitch Current rating Height Stacking height Option A FCI 61082-10260 Receptacle 2x50 0.8mm 0.5A 7.7mm 12mm Option B Tyco 5-5179180-4 Receptacle 2x50 0.8mm 0.5A 7.7mm 12mm Option C Oupiin 2382-100C00DP1T-M Receptacle 2x50 0.8mm 0.5A 7.
PAGE 67
6.5.2 Connectors Pinout The tables below provide complete pinout of extension connector EXT1 and signals mapping. Table 39 – EXT1 connector HOST side pinout EXT-1 connector HOST side Pin # Signal Name Signal Description Pin # Signal Name Signal Description A1 GND Ground connection B1 GND Ground connection A2 SATA2_TX+ B2 CLK1_PCIE+ A3 SATA2_TX- SATA2.
PAGE 68
A34 GND A35 PCIE_TX2+/USB3_TX4+ Ground connection Flexible IO differential transmit pair PCIe2.0 / USB3.0 (up to 5Gbps) PCI Express Wake Event from Device to Host B34 CLK0_OE# PCI Express Clock OE# B35 PCIE_RX2+/USB3_RX4+ B36 PCIE_RX2-/USB3_RX4- Flexible IO differential receive pair PCIe2.0 / USB3.
PAGE 69
6.5.3 FM-USB3 6.5.3.1 Description FM-USB3 FACE Module provide market new USB3.0 Super Speed connectivity, with legacy USB2.0 downstream ports. In addition single mSATA SSD storage card can be implemented via mini PCIe slot either half or full form factors. 6.5.3.2   Highlights 2x USB3.0 downstream ports (USB2.0 supported on separate pins), up to 5Gbps full-duplex. 1x mSATA slot allow to connect mSATA SSD storage (i5/i7 models only). 6.5.3.
PAGE 70
6.5.3.5 Mechanics 6.5.3.5.1 PCB Assembly Figure 20 – FM-USB3 PCB Assembly Top 6.5.3.5.2 Front Panel Figure 21 – FM-USB3 front panel CompuLab Ltd.
PAGE 71
7 Advanced Technologies 7.1 Intel vPRO technology Intel vPRO technology is supported on IPC2 i5 and i7 models only.
PAGE 72
Technology for Directed I/O adds chipset hardware implementation to support and improve I/O virtualization performance and robustness. CompuLab Ltd.
PAGE 73
8 Power Management 8.1 Embedded Controller Renesas H8S/2113 Renesas H8S/2113 embedded controller is an integral part and its HW/FW fully defined by Intel platform architecture. The power manager is a core component in the system and responsible for power management and housekeeping functionality in the platform. It interfaces with processor, chipset, boot devices, system power supplies and power sequencing logic. It is essential part for proper system operation.
PAGE 74
9 Electrical Characteristics 9.1 Absolute Maximum Ratings Operating the IPC2 under conditions beyond its absolute maximum ratings may damage the device. Absolute maximum ratings are limiting values to be considered individually when all other parameters are within their specified operating ranges. Functional operation and specification compliance under any absolute maximum condition, or after exposure to any of these conditions, are not guaranteed or implied. Exposure may affect device reliability.
PAGE 75
9.4 Power Supply IPC2 wall power supply:   CompuLab Ltd.
PAGE 76
10 Mechanical Characteristics 10.1 Mechanical Drawings 10.1.1 Chassis Figure 23 – IPC2 Isometric Front Figure 24 – IPC2 Isometric Back CompuLab Ltd.
PAGE 77
Figure 25 – IPC2 Front Panel Figure 26 – IPC2 Back Panel CompuLab Ltd.
PAGE 78
Figure 27 – IPC2 Top Figure 28 – IPC2 Bottom CompuLab Ltd.
PAGE 79
Figure 29 – IPC2 service door with mounted HDD/SSD storage drive CompuLab Ltd.
PAGE 80
10.1.2 Single Board Computer Single Board Computers or Open Chassis platforms based on IPC2 HW available for system integration and industrial business applications. Available in both variations with or without FACE Module. SBC HW should be thermally coupled to a passive or active cooling system in order to guarantee proper operation and maximal performance. SBC supplied with a heat plate in order to simplify system integration and provide an easy way to attach it to a heat sink.
PAGE 81
10.1.2.2 Without FACE Module Figure 31 – SBC-iHSW Mechanical Drawing without FACE Module CompuLab Ltd.
PAGE 82
10.2 Environmental IPC2 models available in 3 operating temperature grades – Commercial, Extended and Industrial. Please refer to the table below: Table 43 – Operating Temperature Grades Operating Conditions Commercial Op. Temp.
PAGE 83
11 Resources For more Compulab resources please use the following links: 1. Fit-PC website: http://www.fit-pc.com/web/ 2. IPC2 website: http://www.fit-pc.com/web/products/ipc2/ 3. Wiki pages for additional documentation and driver download: http://www.fit-pc.com/wiki/index.php/Main_Page 4. Forum: http://www.fit-pc.com/forum/index.php?sid=47b935636d5b916b34e9acea453fa815 5. Ordering Information Guide: http://fit-pc.com/download/General/ordering-information-guide.pdf 6.