Service manual

Ultraview 1030/1050 Monitors — Service Manual
3-5
Theory
Main CPU
The Ultraview 1030/1050 uses a 25 MHz version of the Motorola MPC860 processor. The
following are some of the special 860 features:
PowerPC core processor unit
4 KB instruction cache
4 KB data cache
Memory management unit
Watchdog and event timers
Interrupt controller
Programmable chip selects and a DRAM controller for memory and peripheral support
Six high-speed dedicated serial peripheral ports
64 programmable I/O ports
Memory
Flash, DRAM, and SRAM memory are all on the local 860 bus. NVRAM is on the ISA bus.
Flash Memory — Two banks of flash memory are connected to programmable chip selects 0 and
1. Flash memory is used for code storage and is fast enough so that code can be directly executed
out of flash. This memory may be in-circuit programmed. The PCBA can hold 2 to 4 MB, with 4
being typical.
DRAM Memory — Two banks of DRAM are connected to chip selects 2 and 3. All DRAM is 3.3 V
EDO. From 4 to 8 MB of DRAM can be installed, with 8 being typical. The application program is
copied from flash to DRAM upon boot up and is executed from DRAM.
SRAM (GDS) Memory — 256 KB of DRAM are connected to chip select 6. This SRAM holds the
GDS data. It is held up through power interruptions by a super cap typically for 12 minutes.
NVRAM Memory — NVRAM is discussed in the ISA section.
MPC860-PCI Bridge
This is a Spacelabs Medical designed Field Programmable Gate Array (FPGA),
which implements a bus bridge between the MPC860 processor and the PCI bus.
The 860 accesses all PCI and ISA devices through this PCI bridge.
The main functions provided by the MPC860-PCI Bridge are:
Enables the 860 processor to access Memory, I/O, and Configuration address spaces on the
PCI.
Allows PCI peripherals to access DRAM and SRAM memory installed on the 860 processor
bus.
Converts big endian to little endian and vice versa. The PCI bus is little endian; the 860 bus is
big endian.
Performs PCI bus central arbiter function.
Performs 860 processor bus arbitration.