Specifications

ManualsBrandsCompaq ManualsComputer equipmentEvo Workstation w4000 - Convertible Minitower

Technical Reference Guide

For

Compaq Evo D300/D500 Personal Computers and

W4000 Workstations

Covers Small Form Factor, Desktop, and Configurable Minitower Models

Featuring the

Intel Pentium 4 Processor and the 845 Chipset

Summary of content (229 pages)

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Technical Reference Guide For Compaq Evo D300/D500 Personal Computers and W4000 Workstations Covers Small Form Factor, Desktop, and Configurable Minitower Models Featuring the Intel Pentium 4 Processor and the 845 Chipset
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This document is designed to fit into a standard 3-ring binder. Provided below is a title block that can be copied and/or cut out and placed into a slip or taped onto the binder.
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Technical Reference Guide NOTICE © 2002 Compaq Information Technologies Group, L.P. Compaq, the Compaq logo, Deskpro, and Evo are trademarks of the Compaq Information Technologies Group, L.P. iPAQ is a trademark of Compaq Information Technologies Group, L.P. in the United States and other countries. Microsoft, MS-DOS, Windows, Windows NT are trademarks of Microsoft Corporation in the United States and other countries. Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in the U.
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Technical Reference Guide ii Compaq Evo and Workstation Personal Computers Featuring the Intel Pentium 4 Processor Second Edition –- January 2003
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Technical Reference Guide TABLE OF CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................. 1.1 ABOUT THIS GUIDE ................................................................................................................ 1-1 1.1.1 ONLINE VIEWING............................................................................................................ 1-1 1.1.2 HARDCOPY ..........................................
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Technical Reference Guide CHAPTER 4 SYSTEM SUPPORT .............................................................................................................. 4.1 INTRODUCTION....................................................................................................................... 4-1 4.2 PCI BUS OVERVIEW ................................................................................................................ 4-2 4.2.1 PCI BUS TRANSACTIONS.............................................
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Technical Reference Guide 5.6 KEYBOARD/POINTING DEVICE INTERFACE................................................................... 5-16 5.6.1 KEYBOARD INTERFACE OPERATION ...................................................................... 5-16 5.6.2 POINTING DEVICE INTERFACE OPERATION .......................................................... 5-18 5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING .......................... 5-18 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR ......................
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Technical Reference Guide 7.5 CLIENT MANAGEMENT FUNCTIONS ................................................................................ 7-12 7.5.1 SYSTEM ID AND ROM TYPE ....................................................................................... 7-14 7.5.2 EDID RETRIEVE ............................................................................................................. 7-14 7.5.3 TEMPERATURE STATUS .....................................................................................
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Technical Reference Guide APPENDIX D COMPAQ/NVIDIA VANTA LT AGP GRAPHICS CARD ............................................. D.1 INTRODUCTION...................................................................................................................... D-1 D.2 FUNCTIONAL DESCRIPTION................................................................................................ D-2 D.3 DISPLAY MODES .......................................................................................................
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Technical Reference Guide APPENDIX H COMPAQ/MATROX G200 MMS QUAD-HEAD PCI GRAPHICS CARD.................. H.1 INTRODUCTION...................................................................................................................... H-1 H.2 FUNCTIONAL DESCRIPTION................................................................................................ H-2 H.3 DISPLAY MODES ....................................................................................................................
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Technical Reference Guide LIST OF FIGURES FIGURE 2–1. FIGURE 2–2. FIGURE 2–3. FIGURE 2–4. FIGURE 2–5. FIGURE 2–6. COMPAQ EVO PERSONAL COMPUTERS AND WORKSTATIONS ................................................. 2-1 COMPAQ EVO AND WORKSTATIONS, FRONT VIEWS ............................................................... 2-5 COMPAQ DESKPROS, REAR VIEWS ......................................................................................... 2-6 SMALL FORM FACTOR CHASSIS LAYOUT, TOP VIEW .....................
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Technical Reference Guide FIGURE 6–1. FIGURE 6–2. FIGURE 6–3. FIGURE 6–4. FIGURE 6–5. FIGURE 6–6. FIGURE 6–7. POWER DISTRIBUTION AND CONTROL, BLOCK DIAGRAM ...................................................... 6-1 SMALL FORM FACTOR POWER CABLE DIAGRAM .................................................................... 6-5 DESKTOP AND CONFIGURABLE MINITOWER POWER CABLE DIAGRAM .................................. 6-6 LOW VOLTAGE SUPPLY AND DISTRIBUTION DIAGRAM ...............................................
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Technical Reference Guide LIST OF TABLES TABLE 1–1. ACRONYMS AND ABBREVIATIONS ........................................................................................... 1-4 TABLE 2-1. FEATURE DIFFERENCE MATRIX ............................................................................................... 2-2 TABLE 2-2. CHIPSET COMPARISON ........................................................................................................... 2-15 TABLE 2-3. SUPPORT COMPONENT FUNCTIONS .................
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Technical Reference Guide TABLE 5–17. TABLE 5–18. TABLE 5–19. TABLE 5–20. TABLE 5–21. TABLE 5–22. TABLE 5–23. TABLE 5–24. TABLE 5–25. TABLE 5–26. TABLE 5–27. USB INTERFACE CONFIGURATION REGISTERS .................................................................... 5-24 USB CONTROL REGISTERS .................................................................................................. 5-24 USB CONNECTOR PINOUT ..............................................................................................
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Technical Reference Guide TABLE F-1. MATROX MILLENNIUM G450 GRAPHICS DISPLAY MODES ........................................................ F-3 TABLE F-2. MONITOR POWER MANAGEMENT CONDITIONS ........................................................................ F-4 TABLE F-3. DB-15 MONITOR CONNECTOR PINOUT .................................................................................... F-5 TABLE F-4. VIDEO IN CONNECTOR PINOUT ............................................................................
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Technical Reference Guide This page is intentionally blank.
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Technical Reference Guide Chapter 1 INTRODUCTION 1. Chapter 1 INTRODUCTION 1.1 ABOUT THIS GUIDE This guide provides technical information about Compaq Evo D300/D500 small form factor, desktop, and configurable minitower personal computers and W4000 workstations that feature the Intel Pentium 4 processor. This document describes in detail the system’s design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.
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Chapter 1 Introduction 1.2 ADDITIONAL INFORMATION SOURCES For more information on components mentioned in this guide refer to the indicated manufacturers’ documentation, which may be available at the following online sources: ♦ ♦ ♦ ♦ ♦ 1.3 Compaq Computer Corporation: http://www.compaq.com Intel Corporation: http://www.intel.com Standard Microsystems Corporation: http://www.smsc.com Texas Instruments Inc.: http://www.ti.com USB user group: http://www.usb.
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Technical Reference Guide 1.5 NOTATIONAL CONVENTIONS The notational guidelines used in this guide are described in the following subsections. 1.5.1 VALUES Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter “h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.” Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise stated. 1.5.
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Chapter 1 Introduction 1.6 COMMON ACRONYMS AND ABBREVIATIONS Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1–1. Acronyms and Abbreviations Table 1-1.
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Technical Reference Guide Table 1-1.
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Chapter 1 Introduction Table 1-1.
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Technical Reference Guide Table 1-1.
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Chapter 1 Introduction Table 1-1.
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Technical Reference Guide Chapter 2 SYSTEM OVERVIEW 2. Chapter 2 SYSTEM OVERVIEW 2.1 INTRODUCTION Compaq Evo Personal Computers and Compaq Workstations (Figure 2-1) deliver an outstanding combination of manageability, serviceability, and consistency for enterprise environments. Based on the Intel Pentium 4 processor with the Intel 845 Chipset, these systems emphasize performance along with industry compatibility. These models feature architectures incorporating the PCI bus.
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Chapter 2 System Overview 2.2 FEATURES AND OPTIONS This section describes the standard features and available options. 2.2.1 STANDARD FEATURES The following standard features are included on all models: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Intel Pentium 4 processor in PPGA478 (Socket N) package Intel 845 Chipset Support for three PC133 DIMMs (2 DDR DIMMs on select W4000 systems) 3.5 inch, 1.
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Technical Reference Guide 2.2.
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Chapter 2 System Overview 2.3 MECHANICAL DESIGN These systems are available in three form factors: ♦ Small Form Factor – a small-footprint desktop designed for environments where both performance and space are critical issues. Desktop – a low-profile ATX-type desktop that satisfies standard expandability needs. Configurable Minitower – an ATX-type unit providing the most expandability and being adaptable to desktop (horizontal) or floor-standing (vertical) placement.
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Technical Reference Guide 2.3.1 CABINET LAYOUTS 2.3.1.
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Chapter 2 System Overview 2.3.1.
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Technical Reference Guide 2.3.2 CHASSIS LAYOUTS This section describes the internal layouts of the chassis. For detailed information on servicing the chassis refer to the multimedia training CD-ROM and/or the maintenance and service guide for these systems. The chassis layout for the Small Form Factor is shown in Figure 2-4. Service features include: ♦ ♦ Easily-removable card cage assembly. Tilting drive bay assembly (for easy access to processor and memory sockets). PCI Conn. 2 (Slot 2) PCI Conn.
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Chapter 2 System Overview Figure 2-5 shows the layout for the Slim Desktop. Service features include: ♦ ♦ Tilting upper drive bay assembly (for easy access to all drive bays). Easy access to expansion slots and all socketed system board components. PCI Slot 1 PCI Slot 2 PCI Slot 3 Speaker Auxiliary Chassis Fan AGP Slot Back Hood Lock Solenoid (Optional) Power Supply Air Baffle Assembly Smart Cover Sensor Switch Upper Drive Bays (Tilting Assembly) Lower Drive Bays Front Figure 2–5.
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Technical Reference Guide Figure 2-5 shows the layout for the Configurable Minitower in the minitower configuration. Features include: ♦ ♦ Externally accessible drive bay assembly may be configured for minitower (vertical) or desktop (horizontal) position. Easy access to expansion slots and all socketed system board components.
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Chapter 2 System Overview 2.3.3 BOARD LAYOUTS Figure 2-7 shows the system and riser boards for the small form factor unit. 1 2 3 4 5 6 7 8 9 10 11 12 13 32 31 30 29 28 14 27 26 25 15 24 23 22 21 20 19 17 18 System Board PCA# 011466-101 or 011351-001 Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTE: Description System board Audio line in jack Audio line out jack USB connectors (2) Serial port A Network interface connector Battery Parallel port Serial port B Top: Mouse conn.
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Technical Reference Guide Figure 2-7 shows the system and PCI slot expansion boards. The system board (with three PCI slots) is common to both the desktop and the configurable minitower units. The PCI slot expansion board is attached to the system board in the configurable minitower unit to provide a total of 5 PCI slots.
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Chapter 2 System Overview 2.4 SYSTEM ARCHITECTURE The Compaq Evo and Workstation systems covered in this guide feature an architecture based on the Intel Pentium 4 processor and the Intel 845 chipset (Figure 2-9). These models use either PC133 or DDR (PC266) SDRAM for system memory, provide AGP 4X graphics support, and include PCI bus expansion capability. The Intel 845 chipset includes the 82845 MCH designed to support the Pentium 4 processor with an FSB speed of 400 MHz.
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Technical Reference Guide Pentium 4 Processor 400-MHz FSB 845 Chipset Monitor RGB AGP 4X Graphics Controller AGP 4X I/F 82845 GMCH Memory Bus SDRAM Cntlr. System Memory Hub Link Bus Pri. IDE Cntlr. IDE Hard Drive Sec. IDE Cntlr. NIC 82801BA ICH2 USB Cntlr.
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Chapter 2 System Overview 2.4.1 INTEL PENTIUM 4 PROCESSOR The models covered in this guide feature the Intel Pentium 4 processor. This processor is backward-compatible with software written for the Pentium III, Pentium II, Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors. The processor architecture includes a floatingpoint unit, 32-KB first and 512-KB secondary caches, and enhanced performance for multimedia applications through the use of multimedia extension (MMX) instructions.
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Technical Reference Guide 2.4.2 CHIPSET The Intel 845 chipset consists of a Memory Controller Hub (MCH), an enhanced I/O controller hub (ICH2), and a firmware hub (FWH). Table 2-2 lists the integrated functions provided by the chipset. Table 2-2. Chipset Comparison Table 2-2.
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Chapter 2 System Overview 2.4.4 SYSTEM MEMORY Two memory types are used in these systems: ♦ ♦ PC133-based with three DIMM sockets supporting up to 3 gigabytes of SDRAM memory 266-MHz DDR-based with two DIMM sockets supporting up to 2 gigabytes of DDR memory. NOTE: The maximum memory amounts stated above are with 1-GB memory modules using 512 Mb technology DIMMs. Industry-standard SDRAM DIMMs and DDR266 DIMMs are not interchangable in these systems. 2.4.5 MASS STORAGE All models include a 3.5 inch 1.
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Technical Reference Guide 2.4.9 GRAPHICS SUBSYSTEM The 82845 MCH component includes an AGP 4X interface that supports an AGP graphics controller installed in the AGP slot. The AGP slot includes both Type 1 and Type 2 retention mechanisms. Dual-monitor support is possible by adding a PCI graphics card to the standard configuration. Table 2-4 lists the key features of the standard graphics subsystems employed in these systems: Table 2-4. Standard Graphics Subsystem Comparison Table 2-4.
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Chapter 2 System Overview 2.4.10 AUDIO SUBSYSTEM These systems use the integrated AC97 audio controller of the 845 chipset and an AC’97compliant audio codec. These systems include microphone and line inputs and headphone and line outputs. The Desktop and Configurable Minitower models include a 3-watt output amplifier driving an internal speaker.
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Technical Reference Guide Table 2-7. Physical Specifications Table 2-7. Physical Specifications Small Configurable Parameter Form Factor Desktop Minitower [3] Height 3.9 in (9.90 cm) 5.72 in (14.5 cm) 17.65 in (44.8 cm) Width 13.1 in (33.3 cm) 15.25 in (38.7 cm) 6.60 in (16.8 cm) Depth 14.4 in (36.6 cm) 17.90 in (45.5 cm) 16.80 in (42.7 cm) Weight (nom.) [1] 20 lb (9.1 kg) 26 lb (12 kg) 26 lb (12 kg) Maximum Supported Weight [2] 100 lb (45.5 kg) 100 lb (45.5 kg) 100 lb (45.
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Chapter 2 System Overview Table 2-9. Optical Drive Specifications Table 2-9. Optical Drive Specifications Parameter Interface Type Media Type (reading) Media Type (writing) Transfer Rate (Reads) 48x CD-ROM IDE Mode 1,2, Mixed Mode, CD-DA, Photo CD, Cdi, CD-XA N/a 4.
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Technical Reference Guide Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM 3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM 3.1 INTRODUCTION This chapter describes the processor/memory subsystem of Compaq Deskpro Personal Computers featuring the Pentium 4 processor. These systems feature the Pentium 4 processor and the 845 chipset (Figure 3-1). The 82845 MCH component of the 845 chipset supports SDRAM memory of either the standard PC133 or the DDR type, depending on model.
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Chapter 3 Processor/Memory Subsystem 3.2 PENTIUM 4 PROCESSOR These systems each feature an Intel Pentium 4 processor in a FC-PGA478 package mounted with a passive heat sink in a mPGA478B zero-insertion force socket. The mounting socket allows the processor to be easily changed for servicing and/or upgrading. 3.2.1 PROCESSOR OVERVIEW The Intel Pentium 4 processor represents the latest generation of Intel’s IA32-class of processors.
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Technical Reference Guide Figure 3-1 illustrates the internal architecture of the Pentium 4 processor. Pentium 4 Processor Branch Prediction Execution Trace Cache CPU Rapid Exe. Eng. ALUs 128-bit Integer FPU Out-ofOrder Core FSB I/F L1 Data Cache 256-KB 8-Way L2 Adv. Transfer Cache ALU Speed: Core speed x2 Core Speed: 1.4, 1.5, 2.0, 2.2 GHz FSB Speed: 400 MHz (effective data transfer rate) Figure 3–2.
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Chapter 3 Processor/Memory Subsystem The Pentium 4 processor is software-compatible with Celeron, Pentium II, Pentium MMX, Pentium, and x86 processors, but will require the latest versions of operating system software to take advantage of the Streaming SIMD extensions (SSE2). 3.2.2 PROCESSOR UPGRADING All units use mPGA478B ZIF mounting socket and ship with the Pentium 4 processor in a FlipChip (FC-PGA478) package installed with a passive heat sink.
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Technical Reference Guide 3.3 MEMORY SUBSYSTEM These systems support one of two types of memory: single data rate (SDR) SDRAM or double data rate (DDR) SDRAM. The system board determines the type of memory supported: ♦ ♦ SDR SDRAM-based system board: Three 168-pin DIMM sockets that accept PC100 or PC133 (PC133 supplied) DIMMs. DDR SDRAM-based system board: Two 184-pin DIMM sockets that accept PC1600 or PC2100 (PC2100 supplied) DIMMs. NOTE: The two memory types are not interchangeable within a system.
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Chapter 3 Processor/Memory Subsystem The SPD address map is shown below. Table 3–1. SPD Address Map (SDRAM DIMM) Table 3-3. SPD Address Map (SDRAM DIMM) Byte 0 Description No. of Bytes Written Into EEPROM 1 Total Bytes (#) In EEPROM 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NOTES: Memory Type No. of Row Addresses On DIMM No. of Column Addresses On DIMM No.
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Technical Reference Guide Figure 3-4 shows the system memory map. FFFF FFFFh FFE0 0000h FFDF FFFFh FEC1 0000h FEC0 FFFFh FEC0 0000h FEBF FFFFh High BIOS Area (2 MB) 4 GB PCI Memory (18 MB) APIC Config.
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Chapter 3 Processor/Memory Subsystem 3.4 SUBSYSTEM CONFIGURATION The 82815 GMCH component provides the configuration function for the processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2. Table 3–2. Host/PCI Bridge Configuration Registers (GMCH, Function 0) Table 3-4.
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Technical Reference Guide Chapter 4 SYSTEM SUPPORT 4. Chapter 4 SYSTEM SUPPORT 4.1 INTRODUCTION This chapter covers subjects dealing with basic system architecture and covers the following topics: ♦ ♦ ♦ ♦ ♦ ♦ ♦ PCI bus overview (4.2) AGP bus overview (4.3) System resources (4.4) System clock distribution (4.5) Real-time clock and configuration memory (4.6) System management (4.7) Register map and miscellaneous functions (4.
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Chapter 4 System Support 4.2 PCI BUS OVERVIEW NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2. These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles address/data transfers through the identification of devices and functions on the bus.
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Technical Reference Guide Figure 4-1.
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Chapter 4 System Support 4.2.1 PCI BUS TRANSACTIONS The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle.
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Technical Reference Guide Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream PCI bus as identified by bus number bits <23..16>.
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Chapter 4 System Support The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header. 31 24 23 16 15 8 7 Register Index 0 31 24 23 16 15 8 7 0 FCh Device-Specific Area Device-Specific Area 40h 3Ch 38h 34h 30h 2Ch 28h Min. Lat. Min. GNT Int. Pin Int.
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Technical Reference Guide 4.2.2 PCI BUS MASTER ARBITRATION The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus.
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Chapter 4 System Support 4.2.3 OPTION ROM MAPPING During POST, the PCI bus is scanned for devices that contain their own specific firmware in ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3). 4.2.4 PCI INTERRUPTS Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots.
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Technical Reference Guide 4.2.7 PCI CONFIGURATION PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA channel configuration, RTC control, port decode ranges, and power management options. These parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of the ICH2 component and configured through the PCI configuration space registers listed in Table 4-4. Configuration is provided by BIOS at power-up but re-configurable by software.
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Chapter 4 System Support 4.2.8 PCI CONNECTOR B94 B62 A62 A94 B52 A52 B1 B49 A1 A49 Figure 4-4. PCI Bus Connector (32-Bit Type) Table 4-5. PCI Bus Connector Pinout Table 4-5. PCI Bus Connector Pinout Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 — B Signal -12 VDC TCK GND TDO +5 VDC +5 VDC INTBINTDPRSNT1RSVD PRSNT2GND GND RSVD GND CLK GND REQ+5 VDC AD31 AD29 GND AD27 AD25 +3.3 VDC C/BE3AD23 GND AD21 AD19 +3.
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Technical Reference Guide 4.3 AGP BUS OVERVIEW NOTE: For a detailed description of AGP bus operations refer to the AGP Interface Specification Rev. 2.0 available at the following AGP forum web site: http://www.agpforum.org/index.htm The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations.
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Chapter 4 System Support 4.3.1.1 Data Request Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA lines (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers.
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Technical Reference Guide AGP 2X Transfers During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 46). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes (DnB) are latched on the rising edge of AD_STBx.
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Chapter 4 System Support Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s) 4.3.2 AGP CONFIGURATION AGP bus operations require the configuration of certain parameters involving system memory access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device integrated within the north bridge (MCH, device 1) component. The AGP function is, from the PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI configuration registers (Table 4-6).
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Technical Reference Guide 4.3.3 AGP CONNECTOR B94 A94 A66 A1 B66 B1 Figure 4-8. Universal AGP Bus Connector Table 4-7. AGP Bus Connector Pinout Table 4-7.
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Chapter 4 System Support 4.4 SYSTEM RESOURCES This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants. 4.4.1 INTERRUPTS The microprocessor uses two types of hardware interrupts; maskable and nonmaskable.
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Technical Reference Guide 8259 Mode The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259equivalent logic. Table 4-8 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first. Table 4-8. Maskable Interrupt Priorities and Assignments Table 4-8.
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Chapter 4 System Support The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the standard ISA interrupts (IRQn). NOTE: The APIC mode is supported by the Windows NT and Windows 2000 operating systems. Systems running the Windows 95 or 98 operating system will need to run in 8259 mode. Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped registers. These registers are listed in Table 4-9. Table 4-9.
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Technical Reference Guide The NMI Status Register at I/O port 061h contains NMI source and status data as follows: NMI Status Register 61h Bit 7 6 5 4 3 2 1 0 Function NMI Status: 0 = No NMI from system board parity error.
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Chapter 4 System Support 4.4.2 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks. NOTE: This section describes DMA in general.
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Technical Reference Guide The DMA logic is accessed through two types of I/O mapped registers; page registers and controller registers. 4.4.2.1 DMA Page Registers The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA channels. Table 4-11 lists the page register port addresses. Table 4-11. DMA Page Register Addresses Table 4-11.
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Chapter 4 System Support DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only possible between 16-bit memory and 16-bit peripherals. The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus.
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Technical Reference Guide 4.5 SYSTEM CLOCK DISTRIBUTION These systems use an Intel CK-type clock generator and crystal for generating the clock signals required by the system board components. Table 4-13 lists the system board clock signals and how they are distributed. Table 4-13. Clock Generation and Distribution Table 4-13. Clock Generation and Distribution Frequncy Source Destination 66, 100, or 133 MHz CK Processor, MCH 100 or 133 MHz CK DIMM sockets 66 MHz CK ICH2, AGP Graphics Cntlr.
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Chapter 4 System Support 4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 ICH2 component and is MC146818-compatible. As shown in the following figure, the 82801 ICH2 component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area.
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Technical Reference Guide 4.6.2 CMOS ARCHIVE AND RESTORE During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and other system variables) in a portion of the flash ROM. Should the system become un-usable, the last good copy of NVRAM data can be restored with the Power Button Override function. This function is invoked with the following procedure: 1. 2. With the unit powered down, press and release the power button.
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Chapter 4 System Support BIOS function (refer to Chapter 8 for BIOS function descriptions). 4.7 SYSTEM MANAGEMENT This section describes functions having to do with security, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally configured through the Setup utility. 4.7.1 SECURITY FUNCTIONS These systems include various features that provide different levels of security.
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Technical Reference Guide 4.7.1.3 Cable Lock Provision These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock mechanism. 4.7.1.4 I/O Interface Security The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup utility to guard against unauthorized access to a system. In addition, the ability to write to or boot from a removable media drive (such as the diskette drive) may be enabled through the Setup utility.
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Chapter 4 System Support 4.7.2 POWER MANAGEMENT This system provides baseline hardware support of ACPI- and APM-compliant firmware and software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be placed into a reduced power mode either automatically or by user control. The system can then be brought back up (“wake-up”) by events defined by the ACPI specification.
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Technical Reference Guide Table 4-16. System Operational Status LED Indications Table 4-16. System Operational Status LED Indications System Status S0: System on (normal operation) S1: Suspend S3: Suspend to RAM S4: Suspend to disk S5: Soft off Processor not seated CPU thermal shutdown ROM error Power supply crowbar activated System off Power LED Steady green Blinks green @ 1 Hz Blinks green @ 1 Hz Blinks green @ 0.5 Hz Off - clear Steady red Off (system powers down) Blinks red @ 1 Hz Blinks red @ .
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Chapter 4 System Support High and low thermal parameters are programmed into the ASIC by BIOS during POST. If the high thermal parameter is reached then the fan(s) will be turned on full speed and the Thermsignal will be asserted. The asserted Therm- signal can, with the proper software setup, be used by the 82801 ICH2 to initiate an AOL message for transmission over a network (refer to Network Interface Controller subsection in Chapter 5).
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Technical Reference Guide 4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS This section contains the system I/O map and information on general-purpose functions of the ICH2 and I/O controller. 4.8.1 SYSTEM I/O MAP Table 4-17 lists the fixed addresses of the input/output (I/O) ports. Table 4-17. System I/O Map Table 4-17. System I/O Map I/O Port Function 0000..001Fh DMA Controller 1 0020..002Dh Interrupt Controller 1 002E, 002Fh Index, Data Ports to LPC47B367 I/O Controller (primary) 0030..
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Chapter 4 System Support 4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS The LPC47B367 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions uses indexed ports unique to the LPC47B367.
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Technical Reference Guide The systems covered in this guide utilize the following specialized functions built into the LPC 47B367 I/O Controller: ♦ Power/Hard drive LED control – The I/O controller provides color and blink control for the front panel LEDs used for indicating system events as listed below: System Status Power LED HD LED S0: System on (normal operation) Steady green Green w/HD activity S1: Suspend Blinks green @ 1 Hz Off S3: Suspend to RAM Blinks green @ 1 Hz Off S4: Suspend to disk Blinks
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Technical Reference Guide Chapter 5 INPUT/OUTPUT INTERFACES 5. Chapter 5 INPUT/OUTPUT INTERFACES 5.1 INTRODUCTION This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 5.2 Enhanced IDE interface (5.2) Diskette drive interface (5.3) Serial interfaces (5.4) Parallel interface (5.
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Chapter 5 Input/Output Interfaces Hard drives types not found in the ROM’s parameter table are automatically configured as to (soft)type by DOS as follows: Primary controller: drive 0, type 65; drive 1, type 66 Secondary controller: drive 0, type 68; drive 1, type 15 Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive configuration. 5.2.1.1 IDE Configuration Registers The IDE controller is configured as a PCI device with bus mastering capability.
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Technical Reference Guide 5.2.2 IDE CONNECTOR This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined for UATA/33 and higher modes, which require a special 80-conductor cable (supplied) designed to reduce cross-talk. Device power is supplied through a separate connector. Figure 5-1. 40-Pin Primary IDE Connector (on system board). Table 5–3.
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Chapter 5 Input/Output Interfaces 5.3 DISKETTE DRIVE INTERFACE The diskette drive interface supports up to two diskette drives, each of which use a common cable connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch 1.44-MB diskette drive installed as drive A. The drive designation is determined by which connector is used on the diskette drive cable.
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Technical Reference Guide 5.3.1 DISKETTE DRIVE PROGRAMMING Programming the diskette drive interface consists of configuration, which occurs typically during POST, and control, which occurs at runtime. 5.3.1.1 Diskette Drive Interface Configuration The diskette drive controller must be configured for a specific address and also must be enabled before it can be used.
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Chapter 5 Input/Output Interfaces Table 5–5. Diskette Drive Interface Control Registers Table 5-5. Diskette Drive Interface Control Registers Pri. Addr. 3F0h Sec. Addr.
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Technical Reference Guide 5.3.2 DISKETTE DRIVE CONNECTOR This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-6 for the pinout) for diskette drives. Drive power is supplied through a separate connector. 2 1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Figure 5-2. 34-Pin Diskette Drive Connector. Table 5–6. 34-Pin Diskette Drive Connector Pinout Table 5-6.
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Chapter 5 Input/Output Interfaces 5.4 SERIAL INTERFACE All models include two RS-232-C type serial interfaces to transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the LPC47B357 I/O controller component that includes two NS16C550-compatible UARTs. Each UART supports the standard baud rates up through 115200, and also special high speed rates of 239400 and 460800 baud.
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Technical Reference Guide 5.4.2 SERIAL INTERFACE PROGRAMMING Programming the serial interfaces consists of configuration, which occurs during POST, and control, which occurs during runtime. 5.4.2.1 Serial Interface Configuration The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also must be activated before it can be used. Address selection and activation of the serial interface are affected through the PnP configuration registers of the LPC47B357 I/O controller.
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Chapter 5 Input/Output Interfaces 5.4.2.2 Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be directly controlled by software through the I/O-mapped registers listed in Table 5-9. Table 5–9. Serial Interface Control Registers Table 5-9. Serial Interface Control Registers COM1 Addr. 3F8h COM2 Addr.
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Technical Reference Guide 5.5 PARALLEL INTERFACE The legacy-light models include a parallel interface for connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into theLPC47B277 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
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Chapter 5 Input/Output Interfaces 5.5.2 ENHANCED PARALLEL PORT MODE In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used.
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Technical Reference Guide 5.5.4 PARALLEL INTERFACE PROGRAMMING Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime. 5.5.4.1 Parallel Interface Configuration The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account.
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Chapter 5 Input/Output Interfaces 5.5.4.2 Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP).
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Technical Reference Guide 5.5.5 PARALLEL INTERFACE CONNECTOR Figure 5-5 and Table 5-12 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port’s operational mode. Figure 5-4. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5–12. DB-25 Parallel Connector Pinout Table 5-12.
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Chapter 5 Input/Output Interfaces 5.6 KEYBOARD/POINTING DEVICE INTERFACE The keyboard/pointing device interface function is provided by the LPC47B357 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers.
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Technical Reference Guide Control of the data and clock signals is shared by the 8042and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard. After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042. Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5–13.
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Chapter 5 Input/Output Interfaces 5.6.2 POINTING DEVICE INTERFACE OPERATION The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the IRQ12 interrupt. 5.6.
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Technical Reference Guide 5.6.3.2 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes).
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Chapter 5 Input/Output Interfaces Table 5-15 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU. Table 5–15. CPU Commands To The 8042 Table 5-15. CPU Commands To The 8042 Value 20h 60h A4h A5h A6h A7h A8h A9h AAh ABh ADh AEh C0h C2h C3h D0h D1h D2h D3h D4h E0h F0hFFh Command Description Put current command byte in port 60h. Load new command byte. Test password installed.
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Technical Reference Guide 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-16 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5-6. Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis) Table 5–16. Keyboard/Pointing Device Connector Pinout Table 5-16.
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Chapter 5 Input/Output Interfaces 5.7 UNIVERSAL SERIAL BUS INTERFACE The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers of up to 12 Mb/s with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems.
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Technical Reference Guide The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that include two or more of seven field types. ♦ Sync Field – 8-bit field that starts every packet and is used by the receiver to align the incoming signal with the local clock. ♦ Packet Identifier (PID) Field – 8-bit field sent with every packet to identify the attributes (in.
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Chapter 5 Input/Output Interfaces 5.7.2 USB PROGRAMMING Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime. 5.7.2.1 USB Configuration The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is configured using PCI Configuration Registers as listed in Table 5-17. Table 5–17. USB Interface Configuration Registers Table 5-17. USB Interface Configuration Registers PCI Config. Addr.
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Technical Reference Guide 5.7.3 USB CONNECTOR The USB interface provides two series-A connectors on the front panel and, on legacy-free models, three series-A USB connectors on the rear panel. 1 3 2 4 Figure 5-9. Universal Serial Bus Connector Table 5–19. USB Connector Pinout Table 5-19. USB Connector Pinout Pin 1 2 Signal Vcc USB- Description +5 VDC Data (minus) Pin 3 4 Signal USB+ GND Description Data (plus) Ground 5.7.
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Chapter 5 Input/Output Interfaces 5.8 AUDIO SUBSYSTEM The systems covered in this guide come configured with one of two types of audio support: ♦ ♦ Desktop/configurable minitower audio subsystem Small form factor audio subsystem 5.8.1 FUNCTIONAL ANALYSIS A block diagram of the audio subsystem is shown in Figure 5-11.
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Technical Reference Guide PC Beep Audio 82801 ICH2 PCI Bus AC’97 Audio Cntlr.
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Chapter 5 Input/Output Interfaces 5.8.2 AC97 AUDIO CONTROLLER The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the 82801 ICH component and supports the following functions: ♦ ♦ ♦ ♦ ♦ ♦ Read/write access to audio codec registers 16-bit stereo PCM output @ up to 48 KHz sampling 16-bit stereo PCM input @ up to 48 KHz sampling Acoustic echo correction for microphone AC’97 Link Bus ACPI power management 5.8.
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Technical Reference Guide 5.8.4 AUDIO CODEC The audio codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13, analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC).
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Chapter 5 Input/Output Interfaces 5.8.5 AUDIO PROGRAMMING Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime. 5.8.5.1 Audio Configuration The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the 82801 ICH2. Table 5-21 lists the PCI configuration registers of the audio subsystem. Table 5–21. AC’97 Audio Controller PCI Configuration Registers Table 5-21.
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Technical Reference Guide 5.8.6 AUDIO SPECIFICATIONS The specifications for the integrated AC97 audio subsystem are listed in Table 5-23. Table 5–23. Audio Subsystem Specifications Table 5-23. AC97 Audio Subsystem Specifications Paramemter Sampling Rate Resolution Nominal Input Voltage: Mic In (w/+20 db gain) Line In Impedance: Mic In Line In Line Out Signal-to-Noise Ratio (input to Line Out) Max.
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Chapter 5 Input/Output Interfaces 5.9 NETWORK INTERFACE CONTROLLER These systems include a 10/100 Mbps network interface controller (NIC) consisting of a 82562equivalent controller integrated into the 82801BA ICH2 component coupled with a physical interface (PHY) component and an RJ-45 jack with integral status LEDs (Figure 5-14). The support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or fullduplex modes, and provides auto-negotiation of both mode and speed.
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Technical Reference Guide NOTE: For the WOL and AOL features to function as described in the following paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with the strip turned off, disable WOL and AOL functionality. 5.9.
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Chapter 5 Input/Output Interfaces 5.9.3 POWER MANAGEMENT SUPPORT The NIC features Wired-for-Management (WfM) support providing system wake up from network events (WOL) as well as generating system status messages (AOL) and supports both APM and ACPI power management environments. The controller receives 3.3 VDC (auxiliary) power as long as the system is plugged into a live AC receptacle, allowing support of wake-up events occuring over a network while the system is powered down or in a low-power state. 5.
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Technical Reference Guide 5.9.4 NIC PROGRAMMING Programming the NIC consists of configuration, which occurs during POST, and control, which occurs at runtime. 5.9.4.1 Configuration The network interface function is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in the following table: Table 5–25. NIC Controller PCI Configuration Registers Table 5-25.
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Chapter 5 Input/Output Interfaces 5.9.5 NIC CONNECTOR Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly. Activity LED Speed LED Pin 1 2 3 6 Description Transmit+ TransmitReceive+ Receive- 8 7 6 5 4 3 2 1 Figure 5-14. Ethernet TPE Connector (RJ-45, viewed from card edge) 5.9.6 NIC SPECIFICATIONS Table 5–27. 82559 NIC Operating Specifications Table 5-27.
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Technical Reference Guide 5.9.7 NIC UPGRADING/CHANGING The integrated NIC may be used in conjunction with another NIC card in a PCI slot. These systems provide AOL support for NIC cards that are AOL-compliant to the extent described previously in section 5.9.2. These systems also provide Remote System Alert (RSA) support for such NIC cards as the 3Com 3C905C-TX NIC card. The RSA function is similar to AOL in that the unit provides, even while powered off, system status alert messages to a network console.
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Chapter 5 Input/Output Interfaces Reportable RSA events are listed in the following table: Table 5–28. Remote System Alert Events Table 5-28. Remote System Alert Events Event Description BIOS Failure Thermal Condition System fails to boot successfully. Thermal ASIC reports high temperature. Some systems may generate an alert message when increasing fan speed. Smart Cover (hood) Sensor detected cover removal.
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Technical Reference Guide Chapter 6 POWER and SIGNAL DISTRIBUTION 6. Chapter 6 POWER SUPPLY AND DISTRIBUTION 6.1 INTRODUCTION This chapter describes the power supply and method of general power and signal distribution. Topics covered in this chapter include: ♦ ♦ ♦ 6.2 Power supply assembly/control (6.2) Power distribution (6.3) Signal distribution (6.
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Chapter 6 Power and Signal Distribution 6.2.1 POWER SUPPLY ASSEMBLY These systems feature auto-ranging power supplies with power factor-correction logic. The SFF systems use a 175-watt supply while the desktop and configurable minitower systems employ a 250-watt supply. Tables 6-1 and 6-2 list the specifications of the power supplies. Table 6–1. 175-Watt Power Supply Assembly Specifications Table 6-1. 175-Watt Power Supply Assembly Specifications (PN 243891) Range/ Tolerance Min. Current Loading [1] Max.
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Technical Reference Guide 6.2.2 POWER CONTROL The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When PS On is de-asserted, the Power Supply Assembly is off and all voltages (except +3.3 AUX and +5 AUX) are not generated. Note that the +3.3 AUX and +5 AUX voltages are always produced as long as the system is connected to a live AC source. 6.2.2.
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Chapter 6 Power and Signal Distribution 6.2.2.2 Power LED Indications A dual-color LED located on the front panel (bezel) is used to indicate system power status. The front panel (bezel) power LED provides a visual indication of key system conditions listed as follows: Power LED Steady green Blinks green @ 1 Hz Blinks green @ 2 Hz Blinks green @ 4 Hz Steady red Blinks red @ 0.
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Technical Reference Guide 6.2.3 POWER MANAGEMENT These systems include power management functions designed to conserve energy. These functions are provided by a combination of hardware, firmware (BIOS) and software. The system provides the following power management features: J Intel Pentium III processor with SpeedStep technology J ACPI v1.0b compliant (ACPI modes C1, C2, S1, and S3, ) J API 1.2 compliant J U.S. EPA Energy Star compliant Table 6-1 shows the comparison in power states. Table 6-1.
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Chapter 6 Power and Signal Distribution 6.3 POWER DISTRIBUTION 6.3.1 3.3/5/12 VDC DISTRIBUTION The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies. Figure 6-2 shows the power supply cabling for small form factor series units.
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Technical Reference Guide Figure 6-3 shows the cabling for the desktop and configurable minitower systems. P2 P8 P7, P8 P6 P4 P7 To Drive Assemblies 1 P5 P3 1 P3 Power Supply Assembly (PN 243890) 4 3 2 P2, P4-6 P1 2 3 4 To System Board 2 1 4 3 P1 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 Conn. P1 P1 [1] P2, 4-7 P3 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 +3.3 +3.3 RTN +5 RTN +5 RTN +3.3 -12 RTN PS On RTN RTN RTN +5 GND GND +12 GND GND +12.8 +12.
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Chapter 6 Power and Signal Distribution 6.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION Voltages less than 3.3 VDC including processor core (VccP) voltage are produced through regulator circuitry (Figure 6-4) on the system board. +5 AUX +5 VDC +3.3 VDC +12 VDC Power Supply +3.3 VDC +3 AUX 3.3 DIMM Circuit 3.3 VDC VDDQ (1.5 VDC) AGP PWR DIMMs AGP Bus 2.5 S3 VDC DDR Power Circuitry +1.8 VDC DDR DIMMs +1.4 Ref +5 VDC +12 VDC +12.
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Technical Reference Guide 6.4 SIGNAL DISTRIBUTION Figures 6-5 and 6-6 shows general signal distribution between the main subassemblies of the system units. Chassis Fan Graphics Controller Audio Fan PWR AGP Bus AGP Conn. J40 Cover Sensor Conn. P70 Conn. P6 PCI Bus Riser Conn. J30 Cover Sensor Riser Card (SPN 252298) Cover Lock Solenoid (Optional) Conn. P124 Conn. J4002 12.8 Vcpu 3/5/12 VDC, 3/5AUX Conn. P1 System Board (PCA #011466 or 011351) Fan Cntrl., PS On IDE Data, Cntl Pri. IDE Conn.
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Chapter 6 Power and Signal Distribution Chassis Fan Graphics Controller AGP Bus AGP Connector Audio Cover Sensor [3] Fan PWR Conn. P8 Conn. P6 Cover Lock Solenoid (Optional) Conn. P125 Power On Conn. P124 Conn. P5 [1] Pwr Btn, Pwr/HD LED Conn. P3 12.8 Vcpu 3/5/12 VDC, 3/5AUX Conn. P1 System Board (PCA #011345 or 011348) Fan Cntrl., PS On Power Supply Assembly IDE Data, Cntl Pri. IDE Conn. P20 Sec. IDE Conn. P21 Audio Conn. P7 Dsk. Conn.
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Technical Reference Guide Power Button/LED Header P5 HD LED Cathode 1 HD LED Anode 3 2 PS LED cathode 4 PS LED anode GND 5 M Reset 7 6 PWR Btn 8 GND +5 VDC 9 NC 11 10 Chassis ID0 GND 13 NC 15 Chassis ID1 17 12 GND 16 +5 VDC 18 GND CD ROM Audio Header P7 1 Audio (Left Channel) 2 Ground 3 Ground 4 Audio (right channel) AOL/SOS Header P12 BIOS Fail 1 Not Connected 3 Not Connected 5 Ground 7 2 Not Connected 4 Not Connected 6 Thermal NOTE: No polarity consideration required for connection to speaker
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Technical Reference Guide Chapter 7 BIOS ROM 7. Chapter 8 BIOS ROM 7.1 INTRODUCTION The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power management activities, and the Setup utility.
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Chapter 7 BIOS ROM 7.2 ROM FLASHING The system BIOS firmware is contained in a flash ROM device that can be re-written with BIOS code (using the ROMPAQ utility or a remote flash program) allowing easy upgrading, including changing the splash screen displayed during the POST routine. 7.2.1 UPGRADING Upgrading the BIOS is not normally required but may be necessary if changes are made to the unit’s operating system, hard drive, or processor. All BIOS ROM upgrades are available directly from Compaq.
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Technical Reference Guide 7.2.2 CHANGEABLE SPLASH SCREEN NOTE: A corrupted splash screen may be restored by the user with the ROMPAQ software. Depending on system, changing (customizing) the splash screen is a function may only be available though Compaq PC Customization Services. The splash screen (image displayed during POST) is stored in the BIOS ROM and may be replaced with another image of choice by using the Image Flash utility (Flashi.exe).
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Chapter 7 BIOS ROM 7.3 BOOT FUNCTIONS The BIOS supports various functions related to the boot process, including those that occur during the Power On Self-Test (POST) routine. 7.3.1 BOOT DEVICE ORDER The default boot device order is as follows: 1. 2. 3. 4. CD-ROM drive (EL Torito CD images) Diskette drive (A) Hard drive (C) Network boot The order can be changed in the ROM-based Setup utility (accessed by pressing F10 when so prompted during POST). 7.3.
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Technical Reference Guide 7.3.3 MEMORY DETECTION AND CONFIGURATION This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus to obtain data on the following DIMM parameters: ♦ ♦ ♦ ♦ ♦ Presence Size Type Timing/CAS latency PC133 capability NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific to this system.
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Chapter 7 BIOS ROM 7.4 SETUP UTILITY The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the F10 key is pressed during the time the F10 prompt is displayed in the lower right-hand corner of the screen during the POST routine. Highlights of the Setup utility are described in the following table.
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Technical Reference Guide Table 7-3. Setup Utility Functions Continued Heading Option Description Storage (continued) Device Configuration (continued) Translation Mode (IDE disks only) Lets you select the translation mode to be used for the device. This enables the BIOS to access disks partitioned and formatted on other systems and may be necessary for users of older versions of Unix (e.g., SCO Unix version 3.2). Options are Bit-Shift, LBA Assisted, User, and None.
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Chapter 7 BIOS ROM Table 7-3. Setup Utility Functions Heading Storage (continued) Option DPS Self-Test Boot Order Security Setup Password Power-On Password Password Options Smart Cover Continued Description Allows user to execute self-tests on IDE hard drives capable of performing the Drive Protection System (DPS) self-tests.
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Technical Reference Guide Table 7-3. Setup Utility Functions Heading Security (continued) Continued Option Master Boot Record Security Save Master Boot Record Restore Master Boot Record Description Allows user to enable or disable Master Boot Record (MBR) Security. When enabled, the BIOS rejects all requests to write to the MBR on the current bootable disk. Each time the computer is powered on or rebooted, the BIOS compares the MBR of the current bootable disk to the previouslysaved MBR.
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Chapter 7 BIOS ROM Table 7-3. Setup Utility Functions Continued Heading Power Option Energy Saver Timeouts Energy Saver Options Advanced (Advanced users only) Power-On Options Onboard Devices PCI Devices Description Allows user to set the energy saver mode (advanced, disable, or minimal). Note: In the minimal energy saver mode setting, the hard drive and system do not go into energy saver mode, but the setting allows you to press the power button to suspend the system.
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Technical Reference Guide Table 7-3. Setup Utility Functions Heading Advanced (continued) Continued Option Bus Options Device Options PCI VGA Configuration Description Allows user to enable or disable: PCI bus mastering, which allows a PCI device to take control of the PCI bus PCI VGA palette snooping, which sets the VGA palette snooping bit in PCI configuration space; this is only needed with more than one graphics controller installed PCI SERR# Generation.
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Chapter 7 BIOS ROM 7.5 CLIENT MANAGEMENT FUNCTIONS Table 7-4 lists the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaqspecific unless otherwise indicated. Table 7-4. Client Management Functions (INT15) Table 7-4.
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Technical Reference Guide To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC locations. The Windows NT extension table is as follows: ; Extension to BIOS SERVICE directory table (next paragraph) db db db dd dw db dd dw “32OS” 2 “$DDC” ? ? “$ERB” ? ? ; sig ; number of entries in table ; DDC POST buffer sig ; 32-bit pointer ; byte size ; ESCD sig ; 32-bit pointer ; bytes size The service identifier for client management functions is “$CLM.
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Chapter 7 BIOS ROM 7.5.1 SYSTEM ID AND ROM TYPE Applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register.
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Technical Reference Guide 7.5.3 TEMPERATURE STATUS The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system’s interior temperature. This function allows an application to check whether the temperature situation is at a Normal, Caution, or Critical condition. 7.5.4 DRIVE FAULT PREDICTION The Compaq BIOS directly supports Drive Fault Prediction for IDE-type hard drives. This feature is provided through two Client Management BIOS calls.
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Chapter 7 BIOS ROM 7.6.1 SMBIOS In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS version 2.3.
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Technical Reference Guide 7.7 POWER MANAGEMENT FUNCTIONS The BIOS ROM provides three types of power management support: independent PM support; APM support, and ACPI support. 7.7.1 INDEPENDENT PM SUPPORT The BIOS can provide power management (PM) of the system independently from an operating system that doesn’t support APM (including DOS, Unix, NT & older versions of OS/2). In the Independent PM environment the BIOS and hardware timers determine when to switch the system to a different power state.
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Chapter 7 BIOS ROM 7.7.1.2 Going to Sleep in Independent PM When a time-out timer expires, Standby for that timer occurs. System Standby When the system acquires the Standby mode the BIOS blanks the screen. Since the hard drive inactivity timer is in the drive and triggered by drive access, the system can be in Standby with the hard drives still spinning (awake). NOTE: The BIOS does not turn the fan(s) off (as on previous products).
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Technical Reference Guide 7.7.2 ACPI SUPPORT This system meets the hardware and firmware requirements for being ACPI compliant. This system supports the following ACPI functions: ♦ ♦ ♦ ♦ ♦ ♦ ♦ PM timer Power button Power button override RTC alarm Sleep/Wake logic (S1,S3, S4 (Windows 2000), S5) C1 state (Halt) PCI Power Management Event (PME) 7.7.3 APM 1.2 SUPPORT Advanced Power Management (APM) is an extension of power management.
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Chapter 7 BIOS ROM Table 7-6. APM BIOS Functions Table 7-6.
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Technical Reference Guide 7.7.3.1 Staying Awake in APM There are two "Time-out to Standby" timers used in APM: the System Timer and the IDE had Drive Timer. System Timer In POST, the ROM enables a timer in the ICH2 that generates an SMI once per minute.
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Chapter 7 BIOS ROM 7.7.3.2 Going to Sleep in APM There are three levels of system sleep in APM: System/Hard Drive Standby, System Suspend, and System Off. System/Hard Drive Standby System Standby is achieved only by a system timer time-out, at such time the following occurs: 1. 2. All APM-aware device drivers put their respective devices into “Device Standby.” The O/S makes a BIOS call to go into System Standby. NOTE: The BIOS ROM of these systems will not turn the fan(s) off as on previous systems).
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Technical Reference Guide System OFF There are two ways to turn the system off: 1. 2. Software shut-down as directed by the O/S. This, being the normal procedure, allows a NIC driver to re-arm the NIC for a Magic Packet™ Press and hold the power button for longer than 4 seconds (not recommended unless necessary). 7.7.3.
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Technical Reference Guide Appendix A ERROR MESSAGES AND CODES A. Appendix A ERROR MESSAGES AND CODES A.1 INTRODUCTION This appendix lists the error codes and a brief description of the probable cause of the error. NOTE: Errors listed in this appendix are applicable only for systems running Compaq BIOS. NOTE: Not all errors listed in this appendix may be applicable to a particular system model and/or configuration. A.2 BEEP/KEYBOARD LED CODES Table A–1. Beep/Keyboard LED Codes Table A-1.
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Appendix A Error Messages and Codes A.3 POWER-ON SELF TEST (POST) MESSAGES Table A–2. Power-On Self Test (POST) Messages Table A-2.
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Technical Reference Guide A.4 SYSTEM ERROR MESSAGES (1xx-xx) Table A–3. System Error Messages Table A-3. System Error Messages Message 101 102 103 104-01 104-02 104-03 105-01 105-02 105-03 105-04 105-05 105-06 105-07 105-08 105-09 105-10 105-11 105-12 105-13 105-14 Probable Cause Option ROM error System board failure (see note) System board failure Master int. cntlr. test fialed Slave int. cntlr. test failed Int. cntlr.
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Appendix A Error Messages and Codes A.5 MEMORY ERROR MESSAGES (2xx-xx) Table A–4. Memory Error Messages Table A-4. Memory Error Messages Message 200-04 200-05 200-06 200-07 200-08 201-01 202-01 202-02 202-03 203-01 203-02 203-03 204-01 204-02 204-03 204-04 204-05 205-01 205-02 205-03 206-xx 207-xx 210-01 210-02 210-03 211-01 211-02 211-03 213-xx 214-xx 215-xx A.
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Technical Reference Guide A.7 PRINTER ERROR MESSAGES (4xx-xx) Table A–6. Printer Error Messages Table A-6. Printer Error Messages A.8 Message 401-01 402-01 402-02 402-03 402-04 Probable Cause Printer failed or not connected Printer data register failed Printer control register failed Data and control registers failed Loopback test failed Message 402-11 402-12 402-13 402-14 402-15 402-05 402-06 402-07 402-08 402-09 402-10 Loopback test and data reg. failed Loopback test and cntrl. reg.
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Appendix A Error Messages and Codes A.9 DISKETTE DRIVE ERROR MESSAGES (6xx-xx) Table A–8. Diskette Drive Error Messages Table A-8.
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Technical Reference Guide A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx) Table A–10. Serial Interface Error Messages Table A-10.
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Appendix A Error Messages and Codes A.12 SYSTEM STATUS ERROR MESSAGES (16xx-xx) Table A–11. System Status Error Messages Table A-11. System Status Error Messages Message 1601-xx 1611-xx Probable Cause Temperature violation Fan failure A.13 HARD DRIVE ERROR MESSAGES (17xx-xx) Table A–12. Hard Drive Error Messages Table A-12. Hard Drive Error Messages Message Probable Cause Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-51 Failed I/O read test 17xx-02 Exceeded max.
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Technical Reference Guide A.14 HARD DRIVE ERROR MESSAGES (19xx-xx) Table A–13. Hard Drive Error Messages Table A-13.
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Appendix A Error Messages and Codes A.16 AUDIO ERROR MESSAGES (3206-xx) Table A–15. Audio Error Messages Table A-15. Audio Error Message Message 3206-xx Probable Cause Audio subsystem internal error A.17 DVD/CD-ROM ERROR MESSAGES (33xx-xx) Table A–16. DVD/CD-ROM Drive Error Messages Table A-16. DVD/CD-ROM Drive Error Messages Message Probable Cause 3301-xx Drive test failed 3305-XX Seek test failed See Table A-18 for additional messages. A.18 NETWORK INTERFACE ERROR MESSAGES (60xx-xx) Table A–17.
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Technical Reference Guide A.19 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx) Table A–18. SCSI Interface Error Messages Table A-18.
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Technical Reference Guide Appendix B ASCII CHARACTER SET B. Appendix B ASCII CHARACTER SET B.1 INTRODUCTION This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol.
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Appendix B ASCII Character Set Table B-1.
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Technical Reference Guide Appendix C KEYBOARD C. Appendix C KEYBOARD C.1 INTRODUCTION This appendix describes the Compaq keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions. This appendix covers the following keyboard types: ♦ Standard enhanced keyboard.
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Appendix C Keyboard C.2 KEYSTROKE PROCESSING A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power (+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated.
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Technical Reference Guide C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer.
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Appendix C Keyboard C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide). Packets received at the system’s USB I/F and decoded as originating from the keyboard result in an SMI being generated.
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Technical Reference Guide C.2.3 KEYBOARD LAYOUTS Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems. Actual styling details including location of the Compaq logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary. C.2.3.
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Appendix C Keyboard C.2.3.2 Windows Enhanced Keyboards 1 18 17 2 3 4 5 19 20 21 22 41 40 39 59 75 92 61 60 93 110 47 46 27 68 83 82 10 11 28 29 50 48 49 67 66 81 80 9 26 25 65 64 79 78 24 45 44 8 7 23 63 62 77 76 43 42 6 94 95 13 31 30 51 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 70 69 84 12 87 86 85 96 111 112 97 98 99 100 38 58 91 101 Figure C–5. U.S.
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Technical Reference Guide C.2.3.3 Easy Access Keyboards The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. Depending on system, either a 7-button or an 8-button layout may be supplied. The 7-button Easy Access Keyboard uses the layout shown in Figure C-7 and is available with either a legacy PS/2-type connection or a Universal Serial Bus (USB) type connection.
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Appendix C Keyboard C.2.4 KEYS All keys generate a make code (when pressed) and a break code (when released) with the exception of the Pause key (pos. 16), which produces a make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
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Technical Reference Guide C.2.4.2 Multi-Keystroke Functions Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions 55-57, 72, 74, 88-90, 100, and 101.
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Appendix C Keyboard C.2.4.4 Easy Access Keystrokes The Easy Access keyboards (Figures C-7 and C-8) include additional keys (also referred to as buttons) used to streamline internet access and navigation.
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Technical Reference Guide C.2.5 KEYBOARD COMMANDS Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic). Table C–1. Keyboard-to-System Commands Table C-1. Keyboard-to-System Commands Command Key Detection Error/Over/run BAT Completion BAT Failure Echo Acknowledge (ACK) Resend Keyboard ID Value 00h [1] FFh [2] AAh FCh EEh FAh FEh 83ABh Description Indicates to the system that a switch closure couldn’t be identified.
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Appendix C Keyboard Table C–2. Keyboard Scan Codes Table C-2. Keyboard Scan Codes Key Pos.
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Technical Reference Guide Table C-2.
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Appendix C Keyboard Table C-2. Keyboard Scan Codes (Continued) Key Pos. 81 82 83 84 85 86 87 Legend N M , . / Shift (right) 88 89 90 91 1 2 3 Enter 92 93 94 95 96 97 Ctrl (left) Alt (left) (Space) Alt (right) Ctrl (right) 98 99 100 101 102 103 104 110 0 .
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Technical Reference Guide Table C-2. Keyboard Scan Codes (Continued) Key Pos.
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Appendix C Keyboard C.3 CONNECTORS Two types of keyboard interfaces are used in Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to chapter 5 “Input/Output” of this guide.
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Technical Reference Guide Appendix D COMPAQ/NVIDIA VANTA LT AGP GRAPHICS CARD D. Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card D.1 INTRODUCTION This appendix describes the Compaq/NVIDIA Vanta LT AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot. The Compaq/NVIDIA Vanta LT AGP Graphics card (P/N 192174-002) provides high 2D performance as well as 3D capabilities.
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Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card D.2 FUNCTIONAL DESCRIPTION The Compaq/NVIDIA Vanta LT Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while 8 megabytes of on-board SDRAM stores the main display image.
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Technical Reference Guide D.3 DISPLAY MODES The 2D graphics display modes supported by the Compaq/NVIDIA Vanta LT Graphics Card are listed in Table D-1. Table D-1. NVIDIA Vanta LT 2D Graphics Display Modes Table D-1.
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Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card D.4 SOFTWARE SUPPORT INFORMATION The Compaq/NVIDIA Vanta LT Pro graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes. Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ D.5 Windows 98, 95 Windows NT 4.0, 3.51 Windows 3.11, 3.
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Technical Reference Guide D.6 CONNECTORS There is one connector associated with this graphics card; the monitor connector. NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide. The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner. D.6.1 MONITOR CONNECTOR 9 Figure D-3.
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Technical Reference Guide Appendix E COMPAQ/NVIDIA QUADRO2 EX/MXR AGP GRAPHICS CARDS E. Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards E.1 INTRODUCTION This appendix describes the Compaq/NVIDIA Quadro2 EX and MXR AGP Graphics Cards used in the standard configuration on some models and also available as an option. These cards (layout shown in the following figure) installs in a system’s AGP slot and provide high 2D performance as well as entry-level 3D capabilities.
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards E.2 FUNCTIONAL DESCRIPTION The NVIDIA Quadro2 MXR Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while 32 megabytes of on-board SDRAM stores the main display image.
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Technical Reference Guide E.3 DISPLAY MODES The 2D graphics display modes supported by the NVIDIA Quadro2 MXR Graphics are listed in Table E-1. Table E-1. NVIDIA Quadro2 MXR Graphics Display Modes Table E-1. NVIDIA Quadro2 EX/MXR Graphics Display Modes Max. Refresh Memory Used Resolution Bits per pixel Color Depth Frequency (Hz) [1] For Texture 640 x 480 8 256 240 N/A 640 x 480 16 65K 240 N/A 640 x 480 32 16.7M 240 28.4 MB 800 x 600 8 256 240 N/A 800 x 600 16 65K 240 N/A 800 x 600 32 16.7M 240 26.
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards E.4 SOFTWARE SUPPORT INFORMATION The NVIDIA Quadro2 MXR graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes. Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ E.5 Windows 3.1, 95, 98, 2000, ME Windows NT 4.0, 3.
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Technical Reference Guide E.6 CONNECTORS There are two connectors associated with the graphics subsystem; the display/monitor connector and the Feature connector. NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide. The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner. E.6.
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards This page is intentionally blank.
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Technical Reference Guide Appendix F COMPAQ/Matrox Millennium G450 AGP GRAPHICS CARD F. Appendix F Compaq/Matrox Millennium G450 AGP Graphics Card F.1 INTRODUCTION This appendix describes the Compaq/Matrox Millennium G450 AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot.
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card F.2 FUNCTIONAL DESCRIPTION The Matrox Millennium G450-SD Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while 16 or 32 megabytes of on-board SDRAM stores the main display image.
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Technical Reference Guide F.3 DISPLAY MODES The graphics display modes supported by the Matrox Millennium G450 Graphics are listed in Table F-1. Table F-1. Matrox Millennium G450 Graphics Display Modes Table F-1. Matrox Millennium G450 Graphics Display Modes Max. Vertical Supporting Resolution Bits per pixel Color Depth Refresh Freq. [1] RAMDAC 640 x 480 8 256 85 Hz Primary 640 x 480 16 65K 85 Hz Primary, Secondary 640 x 480 24 16.7M 85 Hz Primary 640 x 480 32 16.
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card F.4 SOFTWARE SUPPORT INFORMATION The Matrox Millennium G450 graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes. Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as: ♦ ♦ ♦ ♦ ♦ ♦ ♦ F.5 Windows 2000 Windows NT 4.
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Technical Reference Guide F.6 CONNECTORS There are three connectors associated with the graphics subsystem; two display/monitor connectors and the Feature connector. NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide. F.6.1 MONITOR CONNECTOR The display/monitor connector is provided for connection of a compatible RGB/analog monitor. 5 4 10 15 3 9 14 2 13 1 7 8 12 6 11 Figure F-3.
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card F.6.2 VIDEO FEATURE CONNECTOR The Video Feature connector allows a video peripheral such as a TV tuner card to provide video input to the graphics card. This interface is compliant with VESA VIP specification 1.1. 26 / Y13 2 / Y1 1 / Z1 25 / Z13 Figure F-4. Feature Connector (26-Pin Header) Table F–4. Video In Connector Pinout Table F-4.
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Technical Reference Guide Appendix G COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER G. Appendix G Compaq/Adaptec SCSI Host Adapter G.1 INTRODUCTION The Compaq/Adaptec 29160N SCSI Host Adapter (Compaq SP# 158364-001) is a PCI peripheral that provides high performance interfacing with compatible SCSI peripherals, typically SCSI hard drives. The card installs in a PCI slot and supports full bus mastering capability. This appendix covers the following subjects: ♦ ♦ ♦ ♦ Functional description (G.
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter G.2 FUNCTIONAL DESCRIPTION A block diagram of the SCSI Adapter is shown in Figure L-2. The adapter’s architecture is based on the AIC-7892 SCSI controller working off the 32-bit, 66-/33-MHz PCI bus. Providing full bus mastering capability, the adapter supports data transfers up to 266 MB/s using the burst mode rate on a 66-MHz 32-bit PCI bus.
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Technical Reference Guide G.3 SCSI ADAPTER PROGRAMMING G.3.1 SCSI ADAPTER CONFIGURATION The Adaptec SCSI Host Adapter Card is a PCI device and configured using PCI protocol and PCI Configuration Space registers (PCI addresses 00h-FFh) as discussed in Chapter 4 of this guide. Configuration is accomplished by BIOS during POST and re-configurable with software. The vender ID and device ID for the adapter are as follows: Vender ID (PCI config. addr. 00h): 9005h Device ID (PCI config, addr. 02h): 0080h G.3.
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter G.5 SCSI CONNECTORS This SCSI card provides two internal header-type connectors (one 50-pin, one 68-pin) and one external D-type connector (50-pin). G.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR The card provides one external 50-pin D-type Ultra SCSI connector. External cabling should meet T-10 SPI-2 standards (50-conductor, round shielded). Pin 1 Figure G–3. External Ultra SCSI Connector (50-pin) Table G–3.
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Technical Reference Guide G.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR The card provides one internal 50-pin header-type Ultra SCSI connector. Internal cabling to this connector should consists of an unshielded connector with a 50-conductor flat cable as specified in ANSI standard X3T9.2/375R. Pin 1 Pin 49 Pin 2 Pin 50 Figure G–4. Internal 50-Pin Ultra SCSI Connector Table G–4. Internal 50-Pin Ultra SCSI Connector Pinout Table G-4.
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter G.5.3 INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR The card provides one internal 68-pin Ultra160 SCSI connector. This connection is designed for a 68-conductor unshielded Twist ‘N Flat cable as specified in the T-10 SPI-2 standard. Pin 34 Pin 1 Pin 68 Pin 35 Figure G–5. Ultra 160 SCSI Connector (68-pin header type) Table G–5. Ultra160 SCSI Connector Pinout Table G-5.
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Technical Reference Guide Appendix H COMPAQ/Matrox G200 MMS Quad-Head PCI GRAPHICS CARD H. Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card H.1 INTRODUCTION This appendix describes the Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s PCI slot.
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card H.2 FUNCTIONAL DESCRIPTION The Matrox G200 MMS Quad-Head PCI Graphics Card provides high performance, multimonitor 2D imaging. With four G200 graphics controllers each supported with an 8-MB SGRAM frame buffer, the card can provide, with appropriate OS, separate images on up to four displays. Each controller can drive either an analog RGB monitor or a digital video interface-compliant monitor (but not both).
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Technical Reference Guide The card includes four MGA G200 graphics controllers. Each controller includes a VGA controller core, 2D and 3D engines, and a 250-MHz RAMDAC. Each controller can drive either an analog RGB monitor or a DVI-compliant digital monitor.
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card H.3 DISPLAY MODES The graphics display modes supported by each monitor port on the Matrox G200 MMS Graphics card are listed in Table H-1. Table H-1. Matrox G200 MMS Graphics Display Modes Table H-1. Matrox G200 MMS Graphics Controller Display Modes Max. Vertical Monitor Resolution Bits per pixel Color Depth Refresh Freq. [1] Support 640 x 480 8 256 200 Hz Analog or Digital 640 x 480 16 65K 200 Hz Analog or Digital 640 x 480 24 16.
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Technical Reference Guide H.4 DISPLAY CONFIGURATION H.4.1 SINGLE-CARD CONFIGURATION The Matrox G200 MMS Quad-Head PCI Graphics Card supports multiple monitors through the use of adapter cables. The graphics card as ordered from Compaq comes with either an analog adapter cable or a digital adapter cable, depending on order number.
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card H.6 POWER MANAGEMENT AND CONSUMPTION This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table H-2 lists the monitor power conditions. Table H-2. Monitor Power Management Conditions Table H-2.
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Technical Reference Guide H.7 CONNECTORS There are four types of connectors associated with the graphics card; an analog monitor connector, digital monitor connector, adapter cable connectors and the card edge connector. NOTE: The graphic card’s edge connector mates with a PCI slot connector on the system board. This interface is described in chapter 4 of this guide. H.7.1 ADAPTER CABLE CONNECTOR A display or monitor cannot be attached directly to the graphics card.
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card H.7.2 ANALOG MONITOR CONNECTOR The analog adapter cable supplied with the analog version of the graphics card kit provides two DB-15 VGA monitor connectors. 5 4 10 15 3 9 14 2 13 1 7 8 12 6 11 Figure H-5. Analog (VGA) Monitor Connector (One of two female DB-15 connectors). Table H-4. DB-15 Monitor Connector Pinout Table H-4.
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Technical Reference Guide H.7.3 DIGITAL MONITOR CONNECTOR The digital adapter cable supplied with the digital version of the graphics card kit provides two DVI-D monitor connectors. P9 P8 P1 P16 P17 P24 Figure H-6. DVI-D Monitor Connector (24-Pin Connector) Table H–5. Video In Connector Pinout Table H-4.
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INDEX I.
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graphics card, NVIDIA Vanta LT, D-1 graphics subsystem, 2-17 graphics, 3D, D-2, E-2, F-2, H-2 Hard drive activity indicator, 4-32 Hub link bus, 4-7 I/O controller (LPC47B34x), 4-31 I/O map, 4-30 IDE interface, 5-1 IDSEL, 4-4 index addressing, 1-3 interface audio, 2-18, 5-26 diskette drive, 5-4 IDE, 5-1 keyboard/pointing device, 5-16 parallel, 2-16, 5-11 serial, 2-16, 5-8 USB, 2-16, 5-22 interrupts maskable (IRQn), 4-15 nonmaskable (NMI, SMI), 4-17 interrupts, PCI, 4-7 key (keyboard) functions, C-8 keyboard,
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SMI, 4-18 speaker, 5-26 specifications electrical, 2-18 environmental, 2-18 physical, 2-19 power supply, 6-9, 6-10, 6-11 Specifications 8x CD-ROM Drive, 2-20 Audio subsystem, 5-31 Diskette Drive, 2-19 SCSI Host Adapter, G-3 specifications, system, 2-18 SSE2, 3-2 status, LED, 4-27 system board, 2-10, 2-11 system ID, 7-6, 7-14 system memory, 2-16 system resources, 4-15 system ROM, 7-1 system status indications, 4-27 TAFI, 4-29 temperature status, 7-15 thermal sensing, 4-28 typematic, C-8 UART, 5-8 Universal
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