Microprocessor Reference Manual

vi 21264/EV68A Hardware Reference Manual
5.1.4 VirtualAddressControlRegister–VA_CTL ................................. 5–4
5.1.5 VirtualAddressFormatRegister–VA_FORM................................ 5–5
5.2 IboxIPRs................................................................ 5–6
5.2.1 ITBTagArrayWriteRegister–ITB_TAG ................................... 5–6
5.2.2 ITBPTEArrayWriteRegister–ITB_PTE................................... 5–6
5.2.3 ITBInvalidateAllProcess(ASM=0)Register–ITB_IAP........................ 5–7
5.2.4 ITBInvalidateAllRegister–ITB_IA........................................ 5–7
5.2.5 ITBInvalidateSingleRegister–ITB_IS..................................... 5–7
5.2.6 ProfileMePCRegister–PMPC........................................... 5–8
5.2.7 ExceptionAddressRegister–EXC_ADDR.................................. 5–8
5.2.8 InstructionVirtualAddressFormatRegister—IVA_FORM...................... 5–9
5.2.9 InterruptEnableandCurrentProcessorModeRegister–IER_CM................ 5–9
5.2.10 SoftwareInterruptRequestRegister–SIRR................................. 5–10
5.2.11 InterruptSummaryRegister–ISUM ....................................... 5–11
5.2.12 HardwareInterruptClearRegister–HW_INT_CLR ........................... 5–12
5.2.13 ExceptionSummaryRegister–EXC_SUM.................................. 5–13
5.2.14 PAL Base Register – PAL_BASE . . . ...................................... 5–15
5.2.15 IboxControlRegister–I_CTL............................................ 5–15
5.2.16 IboxStatusRegister–I_STAT............................................ 5–18
5.2.17 IcacheFlushRegister–IC_FLUSH........................................ 5–21
5.2.18 IcacheFlushASMRegister–IC_FLUSH_ASM .............................. 5–21
5.2.19 ClearVirtual-to-PhysicalMapRegister–CLR_MAP........................... 5–21
5.2.20 SleepModeRegister–SLEEP........................................... 5–21
5.2.21 ProcessContextRegister–PCTX......................................... 5–21
5.2.22 PerformanceCounterControlRegister–PCTR_CTL.......................... 5–23
5.3 MboxIPRs............................................................... 5–25
5.3.1 DTBTagArrayWriteRegisters0and1–DTB_TAG0,DTB_TAG1............... 5–25
5.3.2 DTBPTEArrayWriteRegisters0and1–DTB_PTE0,DTB_PTE1............... 5–26
5.3.3 DTBAlternateProcessorModeRegister–DTB_ALTMODE..................... 5–26
5.3.4 DstreamTBInvalidateAllProcess(ASM=0)Register–DTB_IAP................ 5–27
5.3.5 DstreamTBInvalidateAllRegister–DTB_IA................................ 5–27
5.3.6 DstreamTBInvalidateSingleRegisters0and1–DTB_IS0,1................... 5–27
5.3.7 DstreamTBAddressSpaceNumberRegisters0and1–DTB_ASN0,1 ........... 5–28
5.3.8 Memory Management Status Register – MM_STAT ........................... 5–28
5.3.9 MboxControlRegister–M_CTL.......................................... 5–29
5.3.10 DcacheControlRegister–DC_CTL ....................................... 5–30
5.3.11 DcacheStatusRegister–DC_STAT....................................... 5–31
5.4 CboxCSRsandIPRs...................................................... 5–32
5.4.1 CboxDataRegister–C_DATA........................................... 5–33
5.4.2 CboxShiftRegister–C_SHFT ........................................... 5–33
5.4.3 CboxWRITE_ONCEChainDescription .................................... 5–33
5.4.4 CboxWRITE_MANYChainDescription .................................... 5–38
5.4.5 CboxReadRegister(IPR)Description ..................................... 5–41
6 Privileged Architecture Library Code
6.1 PALcodeDescription....................................................... 6–1
6.2 PALmodeEnvironment..................................................... 6–2
6.3 RequiredPALcodeFunctionCodes........................................... 6–3
6.4 Opcodes Reserved for PALcode. . ............................................ 6–3
6.4.1 HW_LDInstruction..................................................... 6–3
6.4.2 HW_STInstruction..................................................... 6–4
6.4.3 HW_RETInstruction ................................................... 6–5
6.4.4 HW_MFPRandHW_MTPRInstructions.................................... 6–6
6.5 InternalProcessorRegisterAccessMechanisms................................. 6–7
6.5.1 IPR Scoreboard Bits. . .................................................. 6–8
6.5.2 HardwareStructureofExplicitlyWrittenIPRs................................ 6–8