Microprocessor Reference Manual

21264/EV68A Hardware Reference Manual v
4.4 VictimDataBuffer......................................................... 4–8
4.5 Cache Coherency . . ....................................................... 4–8
4.5.1 Cache Coherency Basics................................................ 4–8
4.5.2 CacheBlockStates.................................................... 4–9
4.5.3 CacheBlockStateTransitions............................................ 4–10
4.5.4 UsingSysDcCommands................................................ 4–11
4.5.5 DcacheStatesandDuplicateTags........................................ 4–13
4.6 LockMechanism.......................................................... 4–14
4.6.1 In-OrderProcessingofLDx_L/STx_CInstructions ............................ 4–15
4.6.2 InternalEvictionofLDx_LBlocks.......................................... 4–15
4.6.3 LivenessandFairness.................................................. 4–15
4.6.4 ManagingSpeculativeStoreIssueswithMultiprocessorSystems ................ 4–16
4.7 SystemPort.............................................................. 4–16
4.7.1 SystemPortPins...................................................... 4–17
4.7.2 ProgrammingtheSystemInterfaceClocks.................................. 4–18
4.7.3 21264/EV68A-to-System Commands ...................................... 4–19
4.7.3.1 BankInterleaveonCacheBlockBoundaryMode ......................... 4–19
4.7.3.2 PageHitMode .................................................... 4–20
4.7.4 21264/EV68A-to-System Commands Descriptions . ........................... 4–21
4.7.5 ProbeResponse Commands (Command[4:0] = 00001) . . . ...................... 4–24
4.7.6 SysAckand21264/EV68A-to-SystemCommandsFlowControl.................. 4–25
4.7.7 System-to-21264/EV68A Commands ...................................... 4–26
4.7.7.1 Probe Commands (Four Cycles) ...................................... 4–26
4.7.7.2 Data Transfer Commands (Two Cycles)................................. 4–28
4.7.8 DataMovementInandOutofthe21264/EV68A.............................. 4–30
4.7.8.1 21264/EV68A Clock Basics .......................................... 4–30
4.7.8.2 FastDataMode ................................................... 4–31
4.7.8.3 FastDataDisableMode............................................. 4–33
4.7.8.4 SysDataInValid_LandSysDataOutValid_L .............................. 4–34
4.7.8.5 SysFillValid_L..................................................... 4–35
4.7.8.6 Data Wrapping . . .................................................. 4–36
4.7.9 NonexistentMemoryProcessing.......................................... 4–38
4.7.10 OrderingofSystemPortTransactions...................................... 4–40
4.7.10.1 21264/EV68A Commands and System Probes ........................... 4–40
4.7.10.2 System Probes and SysDc Commands ................................. 4–42
4.8 BcachePort.............................................................. 4–42
4.8.1 BcachePortPins...................................................... 4–43
4.8.2 BcacheClocking ...................................................... 4–44
4.8.2.1 SettingthePeriodoftheCacheClock .................................. 4–45
4.8.3 BcacheTransactions................................................... 4–47
4.8.3.1 BcacheDataReadandTagReadTransactions .......................... 4–47
4.8.3.2 BcacheDataWriteTransactions ...................................... 4–48
4.8.3.3 BubblesontheBcacheDataBus...................................... 4–49
4.8.4 PinDescriptions....................................................... 4–50
4.8.4.1 BcAdd_H[23:4] . . .................................................. 4–51
4.8.4.2 BcacheControlPins................................................ 4–51
4.8.4.3 BcDataInClk_HandBcTagInClk_H .................................... 4–53
4.8.5 BcacheBanking....................................................... 4–53
4.8.6 Disabling the Bcache for Debugging . ...................................... 4–53
4.9 Interrupts................................................................ 4–54
5 Internal Processor Registers
5.1 EboxIPRs............................................................... 5–3
5.1.1 CycleCounterRegister–CC............................................. 5–3
5.1.2 CycleCounterControlRegister–CC_CTL.................................. 5–3
5.1.3 VirtualAddressRegister–VA............................................ 5–4