Microprocessor Reference Manual

iv 21264/EV68A Hardware Reference Manual
2.3.1 InstructionGroupDefinitions............................................. 2–17
2.3.2 EboxSlotting ......................................................... 2–18
2.3.3 InstructionLatencies ................................................... 2–20
2.4 InstructionRetireRules..................................................... 2–21
2.4.1 Floating-PointDivide/SquareRootEarlyRetire............................... 2–22
2.5 RetireofOperateInstructionsintoR31/F31..................................... 2–22
2.6 LoadInstructionstoR31andF31............................................. 2–23
2.6.1 NormalPrefetch:LDBU,LDF,LDG,LDL,LDT,LDWU,HW_LDLInstructions....... 2–23
2.6.2 PrefetchwithModifyIntent:LDSInstruction ................................. 2–23
2.6.3 Prefetch,EvictNext:LDQandHW_LDQInstructions.......................... 2–24
2.7 SpecialCasesofAlphaInstructionExecution.................................... 2–24
2.7.1 LoadHitSpeculation ................................................... 2–24
2.7.2 Floating-PointStoreInstructions .......................................... 2–26
2.7.3 CMOVInstruction...................................................... 2–26
2.8 MemoryandI/OAddressSpaceInstructions.................................... 2–27
2.8.1 MemoryAddressSpaceLoadInstructions .................................. 2–27
2.8.2 I/O Address Space Load Instructions. ...................................... 2–27
2.8.3 MemoryAddressSpaceStoreInstructions.................................. 2–28
2.8.4 I/OAddressSpaceStoreInstructions ...................................... 2–29
2.9 MAFMemoryAddressSpaceMergingRules.................................... 2–30
2.10 InstructionOrdering........................................................ 2–30
2.11 ReplayTraps............................................................. 2–31
2.11.1 MboxOrderTraps ..................................................... 2–31
2.11.1.1 Load-LoadOrderTrap .............................................. 2–31
2.11.1.2 Store-LoadOrderTrap.............................................. 2–31
2.11.2 OtherMboxReplayTraps ............................................... 2–32
2.12 I/OWriteBufferandtheWMBInstruction....................................... 2–32
2.12.1 MemoryBarrier(MB/WMB/TBFillFlow) .................................... 2–32
2.12.1.1 MBInstructionProcessing ........................................... 2–33
2.12.1.2 WMBInstructionProcessing.......................................... 2–33
2.12.1.3 TBFillFlow....................................................... 2–34
2.13 Performance Measurement Support—Performance Counters . ...................... 2–35
2.14 Floating-PointControlRegister............................................... 2–35
2.15 AMASKandIMPLVERInstructionValues ...................................... 2–37
2.15.1 AMASK.............................................................. 2–38
2.15.2 IMPLVER............................................................ 2–38
2.16 DesignExamples ......................................................... 2–38
3 Hardware Interface
3.1 21264/EV68A Microprocessor Logic Symbol . . . ................................. 3–1
3.2 21264/EV68A Signal Names and Functions ..................................... 3–3
3.3 PinAssignments.......................................................... 3–8
3.4 MechanicalSpecifications................................................... 3–17
3.5 21264/EV68A Packaging . .................................................. 3–18
4 Cache and External Interfaces
4.1 IntroductiontotheExternalInterfaces.......................................... 4–1
4.1.1 SystemInterface ...................................................... 4–3
4.1.1.1 CommandsandAddresses........................................... 4–4
4.1.2 Second-Level Cache (Bcache) Interface . . . ................................. 4–4
4.2 PhysicalAddressConsiderations............................................. 4–4
4.3 BcacheStructure.......................................................... 4–7
4.3.1 Bcache Interface Signals ................................................ 4–7
4.3.2 SystemDuplicateTagStores............................................. 4–7