Microprocessor Reference Manual

21264/EV68A Hardware Reference Manual iii
Table of Contents
Preface
1 Introduction
1.1 TheArchitecture .......................................................... 1–1
1.1.1 Addressing........................................................... 1–2
1.1.2 Integer Data Types. . . .................................................. 1–2
1.1.3 Floating-PointDataTypes............................................... 1–2
1.2 21264/EV68A Microprocessor Features . . ...................................... 1–3
2 Internal Architecture
2.1 21264/EV68A Microarchitecture . . ............................................ 2–1
2.1.1 InstructionFetch,Issue,andRetireUnit .................................... 2–2
2.1.1.1 Virtual Program Counter Logic . . ...................................... 2–2
2.1.1.2 BranchPredictor................................................... 2–3
2.1.1.3 Instruction-StreamTranslationBuffer................................... 2–5
2.1.1.4 InstructionFetchLogic.............................................. 2–6
2.1.1.5 RegisterRenameMaps ............................................. 2–6
2.1.1.6 Integer Issue Queue ................................................ 2–6
2.1.1.7 Floating-Point Issue Queue .......................................... 2–7
2.1.1.8 Exception and Interrupt Logic . . . ...................................... 2–8
2.1.1.9 Retire Logic....................................................... 2–8
2.1.2 Integer Execution Unit .................................................. 2–8
2.1.3 Floating-PointExecutionUnit............................................. 2–10
2.1.4 ExternalCacheandSystemInterfaceUnit .................................. 2–11
2.1.4.1 VictimAddressFileandVictimDataFile ................................ 2–11
2.1.4.2 I/OWriteBuffer.................................................... 2–11
2.1.4.3 Probe Queue...................................................... 2–11
2.1.4.4 DuplicateDcacheTagArray.......................................... 2–11
2.1.5 OnchipCaches........................................................ 2–11
2.1.5.1 InstructionCache .................................................. 2–11
2.1.5.2 DataCache....................................................... 2–12
2.1.6 MemoryReferenceUnit................................................. 2–12
2.1.6.1 LoadQueue ...................................................... 2–13
2.1.6.2 StoreQueue...................................................... 2–13
2.1.6.3 MissAddressFile.................................................. 2–13
2.1.6.4 DstreamTranslationBuffer........................................... 2–13
2.1.7 SROMInterface....................................................... 2–13
2.2 PipelineOrganization ...................................................... 2–13
2.2.1 PipelineAborts........................................................ 2–16
2.3 InstructionIssueRules ..................................................... 2–16