Microprocessor Reference Manual

xiv 21264/EV68A Hardware Reference Manual
4–34 Rules for System Control of Cache Status Update Order........................... 4–42
4–35 RangeofMaximumBcacheClockRatios....................................... 4–43
4–36 BcachePortPins.......................................................... 4–43
4–37 BC_CPU_CLK_DELAY[1:0]Values ........................................... 4–45
4–38 BC_CLK_DELAY[1:0]Values................................................ 4–45
4–39 ProgramValuestoSettheCacheClockPeriod(Single-Data)....................... 4–46
4–40 ProgramValuestoSettheCacheClockPeriod(Dual-DataRate).................... 4–46
4–41 Data-Sample/DriveCboxCSRs .............................................. 4–47
4–42 Programming the Bcache to Support Each Size of the Bcache ...................... 4–51
4–43 ProgrammingtheBcacheControlPins......................................... 4–51
4–44 ControlPinAssertionforRAM_TYPEA........................................ 4–51
4–45 ControlPinAssertionforRAM_TYPEB........................................ 4–52
4–46 ControlPinAssertionforRAM_TYPEC........................................ 4–52
4–47 ControlPinAssertionforRAM_TYPED........................................ 4–52
5–1 InternalProcessorRegisters................................................. 5–1
5–2 CycleCounterControlRegisterFieldsDescription................................ 5–4
5–3 VirtualAddressControlRegisterFieldsDescription............................... 5–5
5–4 ProfileMePCFieldsDescription.............................................. 5–8
5–5 IER_CMRegisterFieldsDescription........................................... 5–10
5–6 SoftwareInterruptRequestRegisterFieldsDescription............................ 5–11
5–7 InterruptSummaryRegisterFieldsDescription................................... 5–12
5–8 HardwareInterruptClearRegisterFieldsDescription.............................. 5–13
5–9 ExceptionSummaryRegisterFieldsDescription ................................. 5–14
5–10 PALBaseRegisterFieldsDescription ......................................... 5–15
5–11 IboxControlRegisterFieldsDescription........................................ 5–16
5–12 IboxStatusRegisterFieldsDescription ........................................ 5–19
5–13 IPRIndexBitsandRegisterFields............................................ 5–21
5–14 ProcessContextRegisterFieldsDescription .................................... 5–22
5–15 PerformanceCounterControlRegisterFieldsDescription.......................... 5–23
5–16 PerformanceCounterControlRegisterInputSelectFields.......................... 5–25
5–17 DTBAlternateProcessorModeRegisterFieldsDescription......................... 5–26
5–18 Memory Management Status Register Fields Description .......................... 5–28
5–19 MboxControlRegisterFieldsDescription....................................... 5–30
5–20 DcacheControlRegisterFieldsDescription..................................... 5–31
5–21 DcacheStatusRegisterFieldsDescription...................................... 5–32
5–22 CboxDataRegisterFieldsDescription......................................... 5–33
5–23 CboxShiftRegisterFieldsDescription......................................... 5–33
5–24 CboxWRITE_ONCEChainOrder ............................................ 5–34
5–25 CboxWRITE_MANYChainOrder ............................................ 5–39
5–26 CboxReadIPRFieldsDescription............................................ 5–41
6–1 RequiredPALcodeFunctionCodes ........................................... 6–3
6–2 Opcodes Reserved for PALcode. . ............................................ 6–3
6–3 HW_LDInstructionFieldsDescriptions......................................... 6–4
6–4 HW_STInstructionFieldsDescriptions......................................... 6–5
6–5 HW_RETInstructionFieldsDescriptions ....................................... 6–6
6–6 HW_MFPRandHW_MTPRInstructionsFieldsDescriptions........................ 6–7
6–7 PairedInstructionFetchOrder ............................................... 6–9
6–8 PALcodeExceptionEntryLocations........................................... 6–13
6–9 IPRs Used for Performance Counter Support . . . ................................. 6–18
6–10 AggregateModeReturnedIPRContents....................................... 6–19
6–11 AggregateModePerformanceCounterIPRInputSelectFields...................... 6–20
6–12 CMOVDecomposed....................................................... 6–21
6–13 ProfileMeModeReturnedIPRContents........................................ 6–22
6–14 ProfileMeModePCTR_CTLInputSelectFields.................................. 6–24
7–1 21264/EV68A Reset State Machine Major Operations . . ........................... 7–1
7–2 Signal Pin Reset State . . . .................................................. 7–3
7–3 PinSignalNamesandInitializationState....................................... 7–5
7–4 Power-Up Flow Signals and Their Constraints . ................................. 7–7
7–5 EffectonIPRsAfterFaultReset.............................................. 7–8