Microprocessor Reference Manual

21264/EV68A Hardware Reference Manual xi
Figures
2–1 21264/EV68A Block Diagram ................................................ 2–3
2–2 BranchPredictor.......................................................... 2–4
2–3 LocalPredictor ........................................................... 2–4
2–4 Global Predictor........................................................... 2–5
2–5 ChoicePredictor.......................................................... 2–5
2–6 Integer Execution Unit—Clusters 0 and 1 . ...................................... 2–9
2–7 Floating-PointExecutionUnits ............................................... 2–10
2–8 PipelineOrganization ...................................................... 2–14
2–9 Pipeline Timing for Integer Load Instructions . . . ................................. 2–24
2–10 PipelineTimingforFloating-PointLoadInstructions............................... 2–25
2–11 Floating-PointControlRegister............................................... 2–36
2–12 TypicalUniprocessorConfiguration ........................................... 2–39
2–13 TypicalMultiprocessorConfiguration .......................................... 2–39
3–1 21264/EV68A Microprocessor Logic Symbol . . . ................................. 3–2
3–2 PackageDimensions....................................................... 3–17
3–3 21264/EV68A Top View (Pin Down) ........................................... 3–18
3–4 21264/EV68A Bottom View (Pin Up)........................................... 3–19
4–1 21264/EV68A System and Bcache Interfaces . . ................................. 4–3
4–2 21264/EV68A Bcache Interface Signals . . ...................................... 4–7
4–3 CacheSubsetHierarchy.................................................... 4–9
4–4 System Interface Signals. . .................................................. 4–17
4–5 FastTransferTimingExample ............................................... 4–32
4–6 SysFillValid_LTiming ...................................................... 4–36
5–1 CycleCounterRegister..................................................... 5–3
5–2 CycleCounterControlRegister............................................... 5–3
5–3 VirtualAddressRegister.................................................... 5–4
5–4 VirtualAddressControlRegister.............................................. 5–4
5–5 VirtualAddressFormatRegister(VA_48=0,VA_FORM_32=0).................... 5–5
5–6 VirtualAddressFormatRegister(VA_48=1,VA_FORM_32=0).................... 5–6
5–7 VirtualAddressFormatRegister(VA_48=0,VA_FORM_32=1).................... 5–6
5–8 ITBTagArrayWriteRegister ................................................ 5–6
5–9 ITBPTEArrayWriteRegister................................................ 5–7
5–10 ITBInvalidateSingleRegister................................................ 5–7
5–11 ProfileMePCRegister...................................................... 5–8
5–12 ExceptionAddressRegister ................................................. 5–8
5–13 InstructionVirtualAddressFormatRegister(VA_48=0,VA_FORM_32=0)........... 5–9
5–14 InstructionVirtualAddressFormatRegister(VA_48=1,VA_FORM_32=0)........... 5–9
5–15 InstructionVirtualAddressFormatRegister(VA_48=0,VA_FORM_32=1)........... 5–9
5–16 InterruptEnableandCurrentProcessorModeRegister............................ 5–10
5–17 SoftwareInterruptRequestRegister........................................... 5–11
5–18 InterruptSummaryRegister ................................................. 5–11
5–19 HardwareInterruptClearRegister ............................................ 5–12
5–20 ExceptionSummaryRegister................................................ 5–14
5–21 PALBaseRegister ........................................................ 5–15
5–22 IboxControlRegister....................................................... 5–16
5–23 IboxStatusRegister ....................................................... 5–19
5–24 ProcessContextRegister................................................... 5–22
5–25 PerformanceCounterControlRegister......................................... 5–23
5–26 DTBTagArrayWriteRegisters0and1........................................ 5–25
5–27 DTBPTEArrayWriteRegisters0and1........................................ 5–26
5–28 DTBAlternateProcessorModeRegister ....................................... 5–26
5–29 DstreamTranslationBufferInvalidateSingleRegisters............................ 5–27
5–30 DstreamTranslationBufferAddressSpaceNumberRegisters0and1................ 5–28
5–31 Memory Management Status Register . . . ...................................... 5–28
5–32 MboxControlRegister...................................................... 5–29
5–33 DcacheControlRegister.................................................... 5–31