Specifications

Operation 2-5
➊
When the system powers up, the SROM code is loaded into the I-cache
(instruction cache) on the first available CPU, which becomes the primary
CPU. The order of precedence is CPU0, CPU1, and so on. The primary
CPU attempts to access the PCI bus. If it cannot, either a hang or a failure
occurs, and this is the only message displayed.
➋
The primary CPU interrogates the I
2
C EEROM on the system board and
CPU modules through shared RAM. The primary CPU determines the
CPU and system configuration to jump to.
The primary CPU next checks the SROM checksum to determine the
validity of the flash SROM sectors.
If flash SROM is invalid, the primary CPU reports the error and continues
the execution of the SROM code. Invalid flash SROM must be
reprogrammed.
If flash SROM is good, the primary CPU programs appropriate registers
with the values from the flash data and selects itself as the target CPU to
be loaded.
➌
The primary CPU (usually CPU0) initializes and tests the B-cache and
memory, then loads the flash SROM code to the next CPU. That CPU then
initializes the EV6 (21264 chip) and marks itself as the secondary CPU.
Once the primary CPU sees the secondary, it loads the flash SROM code to
the next CPU until all remaining CPUs are loaded.
➍
The flash SROM performs B-cache tests. For example, the ECC data test
verifies the detection logic for single- and double-bit errors.
➎
The primary CPU initiates all memory tests. The memory is tested for
address and data errors for the first 32 MB of memory. It also initializes
all the “sized” memory in the system.
If a memory failure occurs, an error is reported. An untested memory
array is assigned to address 0 and the failed memory array is deassigned.
The memory tests are re-run on the first 32 MB of memory. If all memory
fails, the “No Memory Available” message is reported and the system halts.
➏
If all memory passes, the primary CPU loads the console and transfers
control to it.