Service manual

Error Registers 3-11
Table 3-5 Miscellaneous Register (Continued)
Name Bits Type
Initial
State Description
ITINTR <7:4> R, W1C 0 Interval timer interrupt
pending – one bit per CPU.
Pin irq<2> is asserted to the
CPU corresponding to a 1 in
this field.
RES <3:2> MBZ, RAZ 0 Reserved.
CPUID <1:0> RO -
ID of the CPU performing the
read.