Service manual

System Overview 1-19
Each type of bus in the system is unique:
• The two memory data buses operate in 256-bit mode passing two hex words (32
bytes) of data between memory and the D-chips per cycle. The bus operates at
83.3 MHz.
• The two CPU data buses operate in “64-bit mode” passing a quadword (8 bytes)
of data between CPU and the D-chips per cycle. Though the CPU data bus is
narrower than the memory data bus, it operates at four times the speed of the
memory data bus at 333 MHz.
• The single CAP bus is a 24-bit wide bidirectional bus that carries commands and
addresses and is also used for transmitting data to and from the C-chip CSRs and
the TIG bus.
• The two PAD buses operate in 32-bit mode passing 8 nibbles per cycle. Two
cycles are required to pass 8 bytes of data. The PAD bus runs at 83.3 MHz.
• The TIG bus handles flash ROM data (system diagnostics and console programs)
and system interrupts.
The cross-bar switch is controlled by the C-chip which synchronizes, along with the
clock, the D-chips, the CPUs, memory, and the P-chips. Figure 1-10 shows the major
data paths through the system.
The C-chip contains:
• Buffers for requests for the P-chips (shared), and each CPU
• Request queues for each memory bank
• A CPU interface for probe and fill requests and issues
• A P-chip interface controller and bridge between PCI commands and addresses
and CPU PIO commands and addresses
• D-chip controllers, one for the PAD bus and one for everything else
The D-chip contains:
• Queues to and from the P-chip, to and from the CPUs, and to and from memory
• Control from the C-chip
The P-chip contains:
• Upstream (away from the PCI) and downstream (toward the PCI) data queues
• Upstream and downstream address queues
• An upstream address state machine for DMA and peer-to-peer reads and writes
• A scatter/gather table for direct mapped and scatter/gather DMA memory access