System information

Power-Up Diagnostics and Display
2-25
2. 12V, 5V, 3.3V, and –12V outputs are energized and stabilized. If the outputs do
not come into regulation, the power-up is aborted and the power supply enters
the latching-shutdown mode.
2.10 Firmware Power-Up Diagnostics
After successful completion of AC and DC power-up sequences, the processor
performs diagnostics to verify system operation, loads the system console, and tests
the core system (CPU, memory, and system board), including all boot path devices.
These tests are performed as two distinct sets of diagnostics:
1. Serial ROM diagnostics—These tests check the basic functionality of the system
and load the console code from the FEPROM on the system board into system
memory.
Failures during these tests are indicated by error beep codes (Table 2-1) and
messages in the console event log (Section 2.2.2).
2. Console firmware diagnostics—These tests are executed by the console code.
They test the core system, including all boot path devices.
Failures during these tests are reported to the console terminal through the
power-up screen or console event log.
2.10.1 Serial ROM Diagnostics
The serial ROM diagnostics are loaded into the CPU's instruction cache from the
serial ROM on the CPU daughter board. The diagnostics test the system in the
following order:
1. The CPU and backup cache on the CPU daughter board.
2. The CPU module's system bus interface.
3. The system bus to PCI bus bridge and system bus to EISA bus bridge. If the PCI
bridge or EISA bridge fails, an error beep code (3-3-1) sounds. Testing
continues despite these errors.
4. The onboard SCSI controller. If the controller fails, an error beep code (3-3-3)
sounds.
5. First 32 Mbytes of memory. If the memory test fails, the failing bank is mapped
out and memory is reconfigured and retested. Testing continues until good
memory is found. If good memory is not found, an error beep code (1-3-3) is
generated and the power-up tests are terminated.
6. The data path to the FEPROM on the system board.