Service manual

System Overview 1-57
Figure 1–24 shows a functional block diagram of the master phase lock loop
daughtercard (MPLL). Each ASIC in the system has an associated MPLL. To
keep tight clock tolerances, the MPLLs are all deskewed so that all have the
same performance.
To synchronize all ASICs in the system, the global reference clock is supplied to
each MPLL in the system; the MPLLs supply the clock to the ASIC that it is
associated with, tests the ASIC’s delay, and then aligns the internal ASIC clock
to the global reference clock. This design keeps all clocks running to within 200
picoseconds of each other.