Service manual

System Overview 1-55
Figure 1–23 shows a functional block diagram of the clock splitter. A clock
splitter module is required in each QBB.
The clock splitter receives the clock sine wave from either the H-switch clock
module or the dual-output clock module and converts it into 48 copies of a
positive ECL clock signal. This PECL clock signal is transmitted to master
phase lock loop (MPLL) modules associated with each ASIC and CPU in the
system clock domain. Each MPLL and ASIC then uses the signal to generate
clock signals locked to the global reference signal. This scheme produces clock
signals that allow transitions to occur at the same time throughout the system
clock domain.
Outputs are switched and controlled by the presence or absence of a module. If
CPU 0 and 1 are present in a QBB and CPU 2 and 3 are absent, then the clock
signals to CPU 0 and 1 are on and the clock signals to CPU 2 and 3 are off.
The clock splitter module is laser trimmed for module to module matching.
Clocks throughout the system clock domain are kept precise by matching etch
lengths and using precision-made modules in generating the clock signals.