Service manual

1-54 AlphaServer GS80/160/320 Service Manual
1.13.3 Clock Splitter Module
The clock splitter module converts the global reference sine wave from
either clock module to 48 identical copies of a positive ECL (PECL)
signal that is distributed to master phase lock loops (MPLL) associated
with ASICs on the system backplane and on modules in the QBB. It
also generates independent clock signals for the I/O domain.
Figure 1– 23 Clock Splitter Module Block Diagram