Service manual

System Overview 1-53
The dual-output clock module is used in 4 or 8P systems only. The module is
mounted on the rear left side wall of the top drawer in GS80 systems and in the
distribution board housing in GS160/320 systems. It generates a global
reference clock signal from which all other system clock signals are derived.
Equal length coax cables carry the clock signal to the clock splitters in each
QBB. The clock splitter produces 48 copies of the signal that are sent to master
phase lock loop (MPLL) devices associated with each ASIC (or CPU) on modules
and on the QBB backplanes. Each MPLL and ASIC then uses the signal to
generate clock signals locked to the global reference signal. This scheme
produces clock signals that allow transitions to occur at the same time
throughout the system clock domain.
Figure 1–22 shows a block diagram of the dual-output clock module. The
module produces two copies of an extremely clean sine wave that is transmitted
to the clock splitter module.
A DIP switch on the module controls the frequency of the global clock reference
signal; the frequency can be set from 40 to 100 MHz in 100 KHz increments.
The dual-output clock output to a given QBB is controlled by the PSM. A clock
signal is output when a QBB is present and on. If QBBx is present and turned
off by the SCM monitor command, the clock signal to QBBx would not be output
and you can remove the coax cable to that QBB without disrupting the clock
output to other QBBs.