Service manual

System Overview 1-51
The H-switch clock module is mounted above the hierarchical switch and
generates a global reference clock signal from which all other system clock
signals are derived. Coax cables carry the clock signal to the clock splitters in
each QBB and to the built-in clock splitter on the H-switch. The clock splitter
produces 48 copies of the signal that are sent to master phase lock loop devices
(MPLL) associated with each ASIC (or CPU) on modules, on the QBB
backplane, and on the H-switch. Each MPLL and ASIC then uses the signal to
generate clock signals locked to the global reference signal. This scheme
produces clock signals that allow transitions to occur at the same time in any
ASIC throughout the system clock domain.
Figure 1–21 shows a block diagram of the H-switch clock module. The module
produces nine copies of an extremely clean sine wave that is transmitted to
clock splitters in QBBs and to the hierarchical switch. The sine wave is phase
and amplitude matched and because of the bandpass filters has low skew and
phase jitter.
A DIP switch on the module controls the frequency of the global clock reference
signal; the frequency can be set from 40 to 100 MHz in 100 KHz increments.
The global reference clock output to a given QBB is controlled by the PSM. A
clock signal is output when a QBB is present and on. If QBBx is present and
turned off by the SCM monitor command, the clock signal to QBBx would not be
output and it would be possible to remove the coax cable to that QBB without
disrupting the clock output to other destinations.
A single LED on the module, when on, indicates that the clock module is
functioning properly. The LED is visible only when the H-switch enclosure is
open.