Service manual

System Overview 1-45
Figure 1–17 is a block diagram of the 21264 Alpha processor chip. The chip’s
architectural features are:
• Four integer execution units (E-box): two are used for address calculations for load
and store instructions and two are used for normal integer calculations
• Two floating-point execution units (F-box) for add, divide, multiply, and square root
• One instruction fetch, issue, and retire unit (I-box)
• A memory reference unit
• A 64-Kbyte instruction cache (I-cache)
• A 64-Kbyte data cache (D-cache)
• An external cache and system interface unit (C-box)
• Two external interfaces: one backup cache data port with a 16-byte bus and one
system port with an 8-byte data bus
The chip contains 15.2 million transistors and is packaged in a 587-pin grid
array carrier. Four instructions can be issued per clock cycle. The design
supports out-of-order instruction execution, branch prediction, and high-speed
access to backup cache and memory. In addition to normal Alpha RISC
instructions, the 21264 processor includes special motion video instructions.