Service manual

System Overview 1-31
Figure 1–14 is a block diagram of the PCI backplane manager (PBM). It is
primarily responsible for monitoring environmental sensors on the backplane
and reporting unsafe conditions. The shaded part of the block diagram is
powered by Vaux and is available for use whenever AC is applied.
The PBM microprocessor controls the x86 bus upon which are various control
and status registers, an interface to the PCA ASIC (Section 1.21.5), and an
interface to the I
2
C bus on the PCI backplane. As seen in the block diagram, the
microprocessor connects to the CSB and is directed by the system control
manager (SCM). In normal operation the PBM monitors the environment and
reports status to the SCM when polled.
Devices on the I
2
C bus are:
• Two monitors, one monitoring voltages, the other monitoring temperatures, fan
speed, and voltages.
• Four 256x8 byte EEPROMs, one on the PCI backplane, one on the standard I/O
module, and one on each of the two remote I/O riser modules. The EEPROMs
contain service information.
The PBM microprocessor also controls 128 Kbytes of operating RAM, 256 Kbytes
of sector-erasable flash EPROM for instruction storage, and the PCI backplane
LEDs visible on the console serial bus ID module at the rear of the PCI box. See
Section 1.21.6.
PBM firmware resides in flash EPROM that can be updated by the SCM
update command or by LFU.
When power is applied to the PCI backplane (Vaux present), the PBM runs
through its self-test. Areas tested are:
• Flash ROM (checksum)
• RAM
• I
2
C bus controller
• I
2
C FRU EEPROM
• LM80 monitor circuits
• Miscellaneous CSRs
• Note that self-test will fail if an error is found in the EEPROM.
See Section 1.21.2 for a description of the PCI backplane where the PBM
resides.