Service manual

C-30 AlphaServer GS80/160/320 Service Manual
Test#
hex
ERROR#
<15:0>
FRU(s) Component(s) Failure Description
Local IOP BIST check test
0001 QBBx
QBBx
IOD0
IOD1
Write Cache BIST failure (slice 0)
0002 Write Cache BIST failure (slice 1)
0003 Read Cache BIST failure (slice 0)
0004 Read Cache BIST failure (slice 1)
2b
Parameters for all error numbers
P1: IOD_ERR_SUM CSR read results P2: IOD_ERR_SUM CSR address
P3: not used P4: not used
Local QSA error line test
Error# = LMNX
X = 1 CE testing
X = 2 UCE testing
N = 1 No IRQ<0>(CE) or IRQ<4> (UCE) interrupts posted to the CPU
N = 2 Incorrect IRQ interrupts posted to the CPU
M = 0 QSD Error Summary CSR (CPUx_CE/UCE_SUM) was correct
M = 1 Invalid CPU ID in CPUx_CE_SUM or CPUx_UCE_SUM
M = 2 No QBB_NUM bits set in CPUx_CE_SUM or CPUx_UCE_SUM
M = 4 Incorrect QBB_NUM set in CPUx_CE_SUM or CPUx_UCE_SUM
M = 8 More than one QBB_NUM bit set in CPUx_CE_SUM or CPUx_UCE_SUM
L = 1 FRU1 is likely the QSD, QSD->CPU path, or CPU
L = 2 FRU1 is likely IOA, QSDy, or IOA->QSDy path (where y=CPU# of Cpu running the test)
L = 4 FRU1 is likely the QSA, WFJ, or QSA->WFJ path
FRU2 is likely the WFJ, IOA, or WFJ->IOA path
Possible Test 2c Error Numbers (decode based on above chart)
101x, 102x
211x, 212x, 221x, 222x, 241x, 242x, 281x, 282x
411x, 412x, 421x, 422x, 441x, 442x, 481x, 482x
2c
Parameters for all error numbers:
P1: Data read (FAST read) from CPUx_CE_SUM or CPUx_UCE_SUM
P2: Address of CPUx_CE_SUM or CPUx_UCE_SUM which was read in P1
P3: Data read from IOP_QBB_ERR_SUM
P4: EV6 ISUM ipr read data