Service manual

Power-Up Diagnostic Error Table C-29
Test#
hex
ERROR#
<15:0>
FRU(s) Component(s) Failure Description
Local directory scratch and BIST check test
Subtest 1: DIR Scratch CSR (DIR_EDC_SUB_ADDR_B) testing
F001 QBBx.DIR DMA,DMD0,DMD1 Write/Read AA’s pattern to
DIR_EDC_SUB_ADDR_B failed
F002 Write/Read 55’s pattern to
DIR_EDC_SUB_ADDR_B failed
F003 Write/Read FF’s pattern to
DIR_EDC_SUB_ADDR_B failed
F004 Write/Read 00’s pattern to
DIR_EDC_SUB_ADDR_B failed
F005 Float 1’s pattern through
DIR_EDC_SUB_ADDR_B failed
F006 Float 0’s pattern through
DIR_EDC_SUB_ADDR_B failed
Subtest 2: DIR BIST check testing
Error# = 00xx where xx<15:0> = bitmask of failing Arrays 0..15
Note: 2-bits per each Array x (0..15) 00 = NO Error 01 = Single-bit error
10 = Double-bit error 11 = Multiple-bit error
Abcd QBBx.DIR DMA,DMD0,DMD1 DIR BIST never completed or EVERY
DIMM failed
00xx QBBx.DIR.DIM J1, J2… ,J8 DIR_SELF_TEST showed failing DIMMs
2a
(2
sub-
tests)
Subtest 1 Parameters for error numbers F00x
P1: Exp: Data written to DIR_EDC_SUB_ADDR_b
P2: Rcvd: Data read back from DIR_EDC_SUB_ADDR_B after the write
P3: Addr: Failing Address (DIR_EDC_SUB_ADDR_B csr)
P4: CPU# (running this test) in <1:0>
Subtest 2 Parameters for error number abcd:
P1: DIR_SELF_TEST_CTL CSR read results
P2: DIR_SELF_TEST_CTL CSR address
P3: Source HARD QBB ID (QBB where the DIRectory resides)
P4: CPU# in bits <1:0> passed from SCM (System Primary flag in bit <7>)
Subtest 2 Parameters for error number 00xx:
P1: DIR_SELF_TEST CSR read results
P2: DIR_SELF_TEST CSR address
P3: <15:0> Bitmask of failing DIR Arrays 0..15
P4: <15:0> Bitmask of DIRectory DIMMs ARRAY 0..15 which are PRESENT