Service manual

C-24 AlphaServer GS80/160/320 Service Manual
Test#
hex
ERROR #
<15:0>
FRU(s) Component(s) Failure Description
Local IOP error testing m = Interrupt type. (m =1 for CE; m =2 for UCE; m =3 for SE)
0001 QBBq.IORy
(y=0,1)
IOA, QSA,
QSD 0,1,2,3
IOA_ERR_SUM error
0002 “ IOD 0,1, QSD
0,1,2,3
IOD_ERR_SUM error
00m3 QBBq WFJ, IOA,
Path
IOP: IOP_*CE bit Not set
00m4 “ “ IOP: IOP_*CE bit set with other bit set too
00m5 QBBq IOA, QSDx,
Path
QSD: Invalid CPU ID in CPUx_*E_SUM CSR
00m6 “ “ QSD: No QBB_NUM bits set in CPUx_*E_SUM
CSR
00m7 “ “ QSD: Proper QBB bit NOT set in
CPUx_*E_SUM
00m8 “ “ QSD: More than 1 QBB bit set in
CPUx_*E_SUM
00m9 For local test
QBBq
For remote test
Drawer: QBBq
System box:
QBBq
QBBq.GP
QSDx, path,
CPUx
WFJ, GP, path
WFJ, path
Path
00mA “ “
CPU: received incorrect IRQ interrupt
24
Parameters for error # = 0001 and 0002 (IOX = IOA or IOD)
P1: Expected Data (written to IO*_ERR_SUM CSR)
P2: Received Data (read from IO*_ERR_SUM CSR)
P3: Failing Address (of IO*_ERR_SUM CSR)
P4: RSVD
Parameters for error # = 00mn; m =1,2,3; 2< n<^xB
P1: Sender info: interrupt type write into IOP_DIAG_SEND_ERR_INT CSR
P2: Sender info: address of IOP_DIAG_SEND_ERR_INT CSR
P3: Receiver info: data read from IOP_QBB_ERR_SUM or CPUx_*E_SUM or CPU
P4: Receiver info: address of receiver (CSR)