Service manual

Power-Up Diagnostic Error Table C-5
Test
# hex
ERROR #
<15:0>
FRU(s) Component(s) Failure Description
B-cache data line test
0001 QBBx.CPUy EV, Bcache Unexpected error write data pttrn to Bcache.
0002 Unexpected error verifying data pttrn written
0003 B-Cache data RAM failure
0004
B-Cache data RAM failure in a check bit
CB0n
Check bit n failure 0<=n<=^xf
4
Parameters error numbers 1,2,3,4 Test runs to completion unless an unexpected error occurs.
P1 mask has the following information: P1 = aabbccdd.nnnnnnnn Where:
Nnnn bits 31:00 number of errors that occurred.
Dd bits 39:32 mask of bad check bits for the LO QW. bit 32=check bit 0, 33=check bit1, etc.
Cc bits 47:40 mask of bad check bits for the HI QW . bit 40=check bit 8, 41=check bit9, etc.
Bb bits 55:48 if FF then a multiple bit error detected in LO QW and code could not determine
failing check bits. This should normally only occur if 2 check bits failed in LO at same time. if 0
then ignore this field, it has no information
Aa bits 63:56 if FF then a multiple bit error detected in HI QW and code could not determine
failing check bits. This should normally only occur if 2 check bits failed in HI at same time. if 0
then ignore this field, it has no information
P2 mask of any data bits in LO (63:00) that failed during the test. If bit set then that bit failed
at least once, if clear then no error. Bit bit 0 = data bit 0, etc... to bit 63 = data bit 63
P3 mask of any data bits in HI (127:64) that failed during the test. If bit set then that bit failed
at least once, if clear then no error. Bit bit 0 = data bit 64, etc... to bit 63 = data bit 127.
P4 mask contains the QW address of the first location that failed. More than one may fail.
Note: P2 identifies bits <63:00> that failed. P3 identifies bits <127:64> that failed. P1 bits
39:32 identifies check bits 7:0 that failed. P1 bits 47:40 identifies check bits 15:8 that failed.
parameters for error number CB0n (0<= n <= ^xF):
P1: Cache Line offset written a data pattern
P2: Read from CBOX registers: synd_1<31:24>, synd_0<23:16>, c_stat<8:4>, c_sts<3:0>
P3: Read from CBOX register: c_addr
P4: Data pattern written to cache line