Service manual

B-36 AlphaServer GS80/160/320 Service Manual
B.10.7 Global (Remote) Inval-to-Dirty and Full Block Write
Transactions
Figure B– 12 Inval-to-Dirty, Full Block Write Coherency Store Flows
Q0: Visit TTT
via GPLink.
Q0
Q0Vic
Q1
Q1
Response
Packet
Q1
Probe
Packet
(Inval)
Q1: Visit TTT,
Dtag and IOP
Tag store, via
ArbBus.
Source QBB
Q0: Visit Directrory
Dtag, TTT and
IOP Tag store
via ArbB us.
Home QBB
Q1: Visit Dtag, TTT and
IOP Tag store
via ArbBus.
QBB of Shared Processor
Remote Inval-to-Dirty and Full Block Write commands use the system
coherency storage elements as illustrated in Figure B–12 and described by the
following sequence of events.
1. All Inval-to-Dirty and Full Block Write commands first visit the TTT via the
GPLink, for the purpose of creating a TTT MAF entry.