Service manual

Cache Coherency B-35
3. Each Change-to-Dirty-type command is then issued to the ArbBus of the
home QBB by means of the QS Arb. It visits:
• The DTag to determine if any of the CPUs in the home QBB have copies
of the addressed block.
• The directory to determine if the Change-to-Dirty will succeed or fail,
and to determine if any other QBBs have copies of the addressed block.
• The IOP tag store to determine if the home IOP has a copy (clean or
dirty) of the addressed block.
• The TTT to determine if the addressed block is in a transient state.
4. The invalidate probe packets resulting from each Change-to-Dirty-type
command are then issued to the ArbBus of any QBB with a shared
processor. As the invalidate is issued to the ArbBus, it visits:
• The DTag to determine which of the CPUs in the QBB have copies of the
addressed block.
• The IOP tag store to determine if the IOP has a copy of the block.
• The TTT to determine if invalidates should be issued to those processors
(CPU and IOP) that have copies of the addressed block.
5. The Q1 response packets resulting from each Change-to-Dirty-type
command is issued to the ArbBus of the requesting processor’s QBB. It
visits:
• The DTag to update the DTag state (only if the requesting processor is a
CPU), and to determine if any of the CPUs in the requesting processor’s
QBB have copies of the addressed block.
• The IOP tag store to update the IOP tag state (only if the requesting
processor is the IOP), and/or to determine if the IOP in the requesting
processor’s QBB has a copy of the addressed block.
• The TTT to clear/update the TTT MAF state and to determine if
invalidates should be issued to those processors (CPU and IOP) that
have copies of the addressed block.