Service manual

Cache Coherency B-31
Remote Read, ReadVic and Fetch commands use the system coherency storage
elements as illustrated in Figure B–9 and described by the following sequence of
events.
1. Each Read-type command first visits the TTT via the GPLink, for the
purpose of creating a TTT MAF entry.
2. Each Read-type command is then issued to the ArbBus of the home QBB by
means of the QS Arb. It visits:
• The DTag to determine if the addressed block is dirty in the home QBB.
• The directory to determine if the addressed block is dirty in another
QBB.
• The IOP tag store to determine if the home IOP has a dirty copy of the
addressed block.
• The TTT to determine if the addressed block is in a transient state.
3. Fwd Rd probe packets resulting from each Read-type command are then
issued to a Dirty Processor via the ArbBus of the QBB of the Dirty
Processor. No coherency storage is consulted for this operation.
4. Q1 response packets resulting from Read-type commands are issued to the
ArbBus of the requesting processor’s QBB. They visit:
• The DTag to update the DTag state (only if the requesting processor is an
CPU).
• The IOP tag store to update the IOP tag state (only if the requesting
processor is the IOP).
• The TTT to clear/update the TTT MAF state.
5. Q2 response packets resulting from Read-type commands are issued to the
ArbBus of the requesting processor’s QBB. They visit:
• The DTag to update the DTag state (only if the requesting processor is a
CPU).
• The IOP tag store to update the IOP tag state (only if the requesting
processor is the IOP).
• The TTT to clear/update the TTT MAF state.