Service manual

Cache Coherency B-29
Local Change-to-Dirty, Shared-to-Dirty, STCChange-to-Dirty, Inval-to-Dirty
and Full Block Write commands use the system coherency storage elements as
shown in Figure B–8 and described by the following sequence of events.
1. Each Change-to-Dirty-type command is first issued to the ArbBus of the
home QBB by means of the QS Arb. It visits:
• The DTag to determine both if the Change-to-Dirty will succeed or
fail, and if any of the CPUs in the home QBB have copies of the
addressed block.
• The directory to determine if any other QBBs have copies of the
addressed block.
• The IOP tag store to determine if the home IOP has a copy (clean or
dirty) of the addressed block.
• The TTT to determine if the addressed block is in a transient state
and to log transient state information.
2. Invalidate probe packets resulting from each Change-to-Dirty-type
command are then issued to the ArbBus of any QBB with a shared
processor. As the Invalidate is issued to the ArbBus, it visits:
• The DTag to determine which of the CPUs in the QBB have copies of
the addressed block.
• The IOP tag store to determine if the IOP has a copy of the block.
• The TTT to determine if invalidates should be issued to those
processors (CPU and IOP) that have copies of the addressed block.
3. Upon return to the requesting processor’s QBB, the Q1 response packet
visits the TTT via the ArbBus, for the purpose of clearing transient state
information.