Service manual

Cache Coherency B-27
Local Read Mod and Read Vic Mod commands use the system coherency storage
elements as shown in Figure B–7 and described by the following events:
1. Each Read Mod-type command is first issued to the ArbBus of the home
QBB by means of the quad switch arbiter. It visits:
• The Dtag to determine both if the addressed block is dirty in the home
QBB and if any of the CPUs in the home QBB have copies of the block.
• The directory to determine both if the addressed block is dirty in
another QBB and if any other QBBs have copies of the addressed block.
• The IOP tag store to determine if the home IOP has a copy (clean or
dirty) of the addressed block.
• The TTT to determine if the addressed block is in a transient state and
to log transient state information.
2. The Fwd Rd Mod probe packets resulting from each Read-type command are
then issued to the ArbBus of the QBB of a dirty processor. The Fwd Rd Mod
is sent directly to the dirty processor without consulting any coherency
storage. As the Fwd Rd Mod packet is issued to the ArbBus, it visits:
• The DTag to determine if any of the CPUs in the dirty processor’s QBB
have copies of the addressed block.
• The IOP tag store to determine if the IOP in the dirty processor’s QBB
has a copy (clean or dirty) of the addressed block.
• The TTT to determine if invalidates should be issued to those processors
(CPU and IOP) that have copies of the addressed block.
3. Invalidate probe packets resulting from each Read Mod-type command are
then issued to the ArbBus of any QBB with a shared processor. As the
invalidate is issued to the ArbBus, it visits:
• The DTag to determine which of the CPUs in the QBB have copies of the
addressed block.
• The IOP tag store to determine if the IOP has a copy of the block.
• The TTT to determine if invalidates should be issued to those processors
(CPU and IOP) that have copies of the addressed block.
4. Upon return to the requesting processor’s QBB, the Q1 response packet
visits the TTT via the ArbBus to clear transient state information.
5. Upon return to the requesting processor’s QBB, the Q2 fill packet is sent
directly to the requesting processor.