Service manual

Cache Coherency B-25
Local Read, ReadVic, and Fetch commands use the system coherency storage
elements as illustrated in Figure B–6 and described by the following sequence of
events.
1. Each Read-type command is first issued to the ArbBus of the home QBB by
means of the QS Arb. It visits:
• The DTag to determine if the addressed block is dirty in the home QBB.
• The directory to determine if the addressed block is dirty in another
QBB.
• The IOP tag store to determine if the addressed block is dirty in the
home IOP.
• The TTT to determine if the addressed block is in a transient state and to
log transient state information.
2. Fwd Rd probe packets resulting from each Read-type command are steered
directly to the identified dirty processor without consulting any coherency
storage.
3. Upon return to the requesting processor’s QBB, a Q1 response packet visits
the TTT via the ArbBus to clear transient state information.
4. Upon return to the requesting processor’s QBB, the Q2 Fill packet is sent
directly to the requesting processor.