Service manual

B-22 AlphaServer GS80/160/320 Service Manual

B.9.6 Access to Coherency State

Figure B–5 shows how the various coherency stores are connected in a QBB.

The PTag is omitted from the diagram because it is connected to, and used

exclusively by, the CPU processor. As can be seen in Figure B–5, the QSA

implements two interfaces to the cache coherency stores. The information in

Table B–10 describes the two interfaces.

Figure B– 5 Cache Coherency Storage Access

S Arb