Service manual

Cache Coherency B-21
B.9.4 QBB Directory
There is one directory store in each QBB in the system. Each directory holds
one entry for each main memory block in its QBB. For example, a 32-Gbyte
memory system consisting of 64-byte blocks would require 512-Mbyte directory
entries.
Table B– 9 Directory Cache Coherency Storage
Directory Field Field Description
Owner-ID
This is a 6 bit encoded field. It identifies which of 32
processors, 8 IOPs or single memory bank holds the most
up to date copy of a memory block.
QBB-Present
This is an 8-bit vector field. It identifies which QBBs in
the system have processors which have up to date, cached
copies of a memory block.
NOTE: Although 8 bits are defined in the directory QBB-
present mask, only 7 are used. The last bit, whichever
corresponds to the home QBB of a given directory, is not
necessary because the DTag in the home QBB tracks the
coherency status of blocks in local processors.
Only the QSA chip, through the QS Arb, accesses the directory. Its primary
function is to provide coherency status in response to requests to local requests.
The QBB directories are the primary coherency store for these systems.
B.9.5 TTT Storage
The transaction tracking table is a fully associative, multifunctional control
structure. There is one TTT in each global port in a system. This structure
performs the following tasks:
1. The TTT acts as a Miss Address File (MAF) for all remote references issued
by its associated QBB. This means that the TTT stores 1 entry of
information for each remote access issued by a QBB until that transaction is
considered complete.
2. The TTT provides coherency information, with regard to transient
coherency states, in response to requests to local addresses.