Service manual

B-18 AlphaServer GS80/160/320 Service Manual
B.9 Coherency Data Storage
Cache coherency information is stored in the following locations in the system:
• The CPU’s primary tag storage (PTag)
• The IOP tag storage
• The duplicate tag storage on the QBB (DTag)
• The transaction tracking table in the global ports (TTT)
B.9.1 CPU Primary Tag Store (PTag)
There is one PTag store in each CPU processor in the system. Each PTag store
has one entry per EV6 cache location. Table B–6 describes the information
stored in the PTag for each cached block on the CPU module.
Table B– 6 CPU PTag Cache Coherency Storage
PTag Field Field Description
Valid
When set, indicates that a memory block is cached at the
associated cache location.
Dirty Indicates that the cached block is writeable.
Shared
Indicates that another processor has a copy of the cached
block.
Tag
Identifies the cached memory block; equivalent to the high
order address bits of the cached block.
Only the CPU chip accesses the Ptag and only under the following
circumstances:
1. When issuing loads and stores, to determine if a copy of a block is in cache
and/or if a cached block is write-able.
2. When responding to probe requests from the system. These probe requests
may be to provide a copy of its block, invalidate its block, or both invalidate
and provide a copy of its block.